The Chip - CMOS PLL calibration techniques

A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications

“…For example, the PLL must settle before a valid control voltage value in the VCO that can be read to make voltage comparison [3,4]. In the other case [5], the counter must accumulate a sufficient amount of counts to ensure certain calibration accuracy. The proposed frequency synthesizer architecture is shown in Fig.…”

“…Owing to the repeated locking process and repeated checking when the PLL settles in a specified frequency sub-band, the technique would take lots of reference cycle to complete the discrete tuning, owing to the repeated PLL locking process and repeated checking when the PLL settles in a specified frequency subband. In [5], the control voltage of the VCO is connected to a reference voltage at first, usually the half of the supply voltage. Then the counter begins to calculate the reference and the divided frequency cycles, and some judgments are done after a specified time.…”

An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL

“…2(a), where the PLL remains closed during calibration [1], [2]. For a VCO embedded in a PLL, the loop works to lock the VCO to a desired frequency under a given VCO frequency sub-band setting.…”

“…In contrast to the closed-loop VCO calibration, the PLL loop is disconnected in the open-loop calibration method [2], [3]. A typical open-loop implementation is illustrated in Fig.…”

Fast frequency calibration of VCO's in phase-locked loops

“…In addition, the PLL loop must settle each time an adjustment is made to the subband control word before Vctrl can be measured leading to long calibration times. An improvement to this approach is presented in [7] where only one loop is employed thus removing er rors arising from mismatches between loops and re ducing area. Nevertheless, the PLL loop still needs time to settle before each measurement of Vctrl, leading to similar prolonged calibration times.…”