An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL

Lin, Tsung-Hsien; Lai, Ying‐Jang

doi:10.1109/jssc.2006.889360

Cited by 117 publications

(48 citation statements)

References 11 publications

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“…To calibrate the process variation of the varactors, D DAC is applied to the 4-bit DAC and its output sets V CTRL to the high VCO gain region before the PLL loop is closed. The total time of NV-M readout and DAC settling in the open-loop calibration is 3.2 μsec, which is smaller than the value (4 μsec) presented in the previous open-loop calibration [4].…”

Section: Pll Start-up Acceleration Techniquesmentioning

confidence: 55%

“…In conventional open-loop VCO tuning techniques, the PLL loop is disconnected at the loop filter output, and VCO control voltage, V CTRL , is connected to a reference voltage (usually V DD /2, where V DD is power supply). During this open-loop period, capacitors used in VCO are tuned to accommodate to each band of operation, and subsequently, the PLL loop is closed for the frequency synthesis [4]. Problems in this open-loop calibration method are that complex frequency detection scheme is required for the agile VCO coarse tuning and the influence of the initial V CTRL setting to V DD /2 are ignored.…”

Section: Introductionmentioning

confidence: 99%

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Fractional-N PLL synthesizer with 15µsec start-up time by on-chip nonvolatile memory

Lee

Masui

2012

IEICE Electron. Express

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Abstract:We propose a fractional-N PLL synthesizer with 15 μsec start-up time featuring an open-loop VCO capacitor coarse setting and subsequent VCO control voltage setting technique with a nonvolatile memory, which can eliminate the frequency detection and VCO coarse tuning sequence used in conventional start-up acceleration techniques. The on-chip nonvolatile memory fabricated in a standard CMOS technology stores the predetermined calibration data to overcome the process variations in VCO capacitors and varactors. A prototype PLL is designed in a standard 0.18 μm CMOS technology with die size of 950 μm x 515 μm and 10.4% area overhead of the acceleration circuits, and presents the measured start-up time of 14.6 μsec.

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Section: Pll Start-up Acceleration Techniquesmentioning

confidence: 55%

Section: Introductionmentioning

confidence: 99%

Fractional-N PLL synthesizer with 15µsec start-up time by on-chip nonvolatile memory

Lee

Masui

2012

IEICE Electron. Express

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“…The proposed calibration algorithm achieves the least calibration time for a resolution of f ref and the finest resolution in a unit reference cycle (T ref ), which is better than all mentioned publications. The proposed fast AFC circuit has no power consumption at steady state, which is an important advantage compared to analog AFCs [5,6]. Area of the proposed AFC is also the smallest compared to mentioned publications, which demonstrated the proposed AFC is the most efficient technique among published fast AFCs.…”

Section: Simulations Resultsmentioning

confidence: 82%

“…8, which proves that an optimum final code is selected after 1.44 µs calibration. [4,5,6,7] is listed in Table II. The proposed AFC achieves the fasted calibration time through the multi-phase sampling algorithm among all counter based AFC techniques [4,7].…”

Section: Simulations Resultsmentioning

confidence: 99%

“…Relative frequency comparison algorithm AFC (counter based) is time inefficient due to its long comparison time [3] and low comparison resolution [4]. Time-to-voltage converter based relative period comparison algorithm is the fastest calibration circuit ever reported [5,6]. However, since it is based on analog voltage comparator, its frequency resolution suffers a lot from analog circuit mismatch, which can not be avoided during circuit implementation.…”

Section: Introductionmentioning

confidence: 99%

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A fast and efficient automatic frequency calibration technique for 10 GHz PLLs

Qin

Zhou

et al. 2014

IEICE Electron. Express

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A fast and efficient automatic frequency calibration (AFC) technique suitable for high frequency PLLs is presented in this paper and a 10 GHz PLL using the proposed AFC circuit is designed in 65 nm CMOS technology. The fast AFC technique is achieved through a multi-phase clock sampling based algorithm which reduces comparison time of each calibration step to at least one reference cycle with small frequency resolution. A dual-mode frequency divider is proposed to save circuit cost for a high frequency multi-phase clock generator. The proposed divider generates 8-phase high frequency clock for the proposed AFC to reduce its calibration time. Simulation results demonstrate that the calibration time is less than 1.44 us for each output frequency. The proposed AFC circuit is competitive among published AFC techniques in calibration time, unit cycle frequency resolution, area cost and power dissipation.

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A fast automatic frequency calibration technique for a 2–6 GHz frequency synthesizer

Jeong¹,

Choi²,

Yoo³

2012

Circuit Theory & Apps

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A fast automatic frequency calibration (AFC) technique is described. For fast AFC operation while eliminating the uncertainty of the initial phase relationship between the reference clock and voltage-controlled oscillator output, two-phase reference clocks are employed. The proposed AFC scheme is applied to a 2-6 GHz frequency synthesizer. The frequency synthesizer is implemented in a 0.18 mm complementary metal-oxidesemiconductor process and occupies 0.92 mm 2 while the AFC occupies only 0.01 mm 2 . The AFC operation is completed in less than 1.6 ms.

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An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL

Cited by 117 publications

References 11 publications

Fractional-N PLL synthesizer with 15µsec start-up time by on-chip nonvolatile memory

Fractional-N PLL synthesizer with 15µsec start-up time by on-chip nonvolatile memory

A fast and efficient automatic frequency calibration technique for 10 GHz PLLs

A fast automatic frequency calibration technique for a 2–6 GHz frequency synthesizer

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