The circuits and physical design of the synergistic processor element of a CELL processor

This paper describes the architecture and implementation of the original gaming-oriented synergistic processor element (SPE) in both 90-nm and 65-nm silicon-on-insulator (SOI) technology and introduces a new SPE implementation targeted for the highperformance computing community. The Cell Broadband Enginee processor contains eight SPEs. The dual-issue, four-way singleinstruction multiple-data processor is designed to achieve high performance per area and power and is optimized to process streaming data, simulate physical phenomena, and render objects digitally. Most aspects of data movement and instruction flow are controlled by software to improve the performance of the memory system and the core performance density. The SPE was designed as an 11-FO4 (fan-out-of-4-inverter-delay) processor using 20.9 million transistors within 14.8 mm 2 using the IBM 90-nm SOI low-k process. CMOS (complementary metal-oxide semiconductor) static gates implement the majority of the logic. Dynamic circuits are used in critical areas and occupy 19% of the non-static random access memory (SRAM) area. Instruction set architecture, microarchitecture, and physical implementation are tightly coupled to achieve a compact and power-efficient design. Correct operation has been observed at up to 5.6 GHz and 7.3 GHz, respectively, in 90-nm and 65-nm SOI technology.

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Section: Figurementioning

confidence: 99%

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

Flachs¹,

Asano²,

Dhong³

et al. 2007

IBM J. Res. & Dev.

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“…Difficulty of design, high power consumption, and the relative ease in synthesizing random logic using standard cells has made PLAs increasingly rare in ICs. However, their high speed continues to make them valuable in very high performance designs [4].…”

Section: Introductionmentioning

confidence: 99%

Circuit architecture for low-power race-free programmable logic arrays

Samson

Clark

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

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The design of programmable logic arrays using NAND-NOR gates for the AND and OR logic planes, respectively, instead of the conventional NOR-NOR planes is described. The circuit architecture uses a hierarchical tree of four input domino NAND gates to implement the AND plane. The OR plane is split in two for increased speed and robustness. The circuits as well as timing and power advantages are described. Simulations on a foundry 130 nm process show nearly 50% power savings at less than 10% delay cost, primarily due to lower AND plane activity factor and reduced clock loading.

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Section: Introductionmentioning

confidence: 99%

A 0.13 μm Low-power Race-free Programmable Logic Array

Samson

Clark

2006

IEEE Custom Integrated Circuits Conference 2006

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A PLA using NAND and NOR gates for the AND and OR logic planes, respectively, is described. The circuit design, timing and power advantages are described. Nearly 50% power savings over a conventional PLA design is achieved on a 130 nm process at less than 10% delay cost. The new PLA circuit has been fabricated on a 130 nm low standby power process and tested silicon operates at 905 MHz at V DD = 1.5 V.

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The circuits and physical design of the synergistic processor element of a CELL processor

Cited by 15 publications

References 7 publications

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

Circuit architecture for low-power race-free programmable logic arrays

A 0.13 μm Low-power Race-free Programmable Logic Array

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The circuits and physical design of the synergistic processor element of a CELL processor

Cited by 15 publications

References 7 publications

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

Circuit architecture for low-power race-free programmable logic arrays

A 0.13 &#x003BC;m Low-power Race-free Programmable Logic Array

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Product

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A 0.13 μm Low-power Race-free Programmable Logic Array