Copper ͑Cu͒ contamination at the wafer bevel, back side surface, and exclusion zone is identified step-by-step following a typical dual-damascene process. The shield ring of a physical vapor deposition system does not protect the exclusion zone and bevel efficiently. Also, Cu may dissolve and accumulate in the solvent used for post dielectric etch clean. Dissolved Cu atoms may then redeposit on the wafer surface. Furthermore, the rough back side surface traps Cu atoms easier than the smooth front side surface. If there is no SiO 2 film on the back side surface, post chemical mechanical polish cleaning using dilute HF cannot remove Cu at the back side surface. An optimized single-wafer spin-etch process was proposed. An optimal etchant consisting of HF, HNO 3 , H 2 SO 4 , and H 3 PO 4 with ratios 0.5:3:1:0.5 showed excellent performance. Experiments demonstrated that a very short, 10 s, back side clean can totally remove Cu from back side surface, bevel, and 2 mm exclusion zone. A ''wafer shift'' procedure was also proposed to solve the pinmark issue near the edge pin due to etchant remnant. The optimized cleaning technique shows shorter process time and higher cleaning efficiency than those reported previously.With the progress of integrated circuit ͑IC͒ processing technology, the feature size is scaled down continuously. As the device performance and the circuit density are improved due to shorter channel length and smaller device geometry, the resistance and capacitance of multilevel interconnects are increased due to the thinner and longer metal wires and the narrower space between them. Copper ͑Cu͒ has been recognized as the most suitable alternative for aluminum as an interconnect material because of its low electrical resistivity and excellent electromigration resistance.