The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best

Sazeides, Yiannakis; Kumar, Rakesh; Tullsen, Dean M.; Constantinou, Theofanis

doi:10.1109/l-ca.2005.2

Cited by 15 publications

(6 citation statements)

References 5 publications

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“…Note that this formula complies with the recommendations by Sazeides et al [2005] regarding how to compute average EDP across benchmarks. (5) We can now compute the normalized EDP ( EDP) of processor configuration j relative to the minimum EDP:…”

Section: Optimization Criterionsupporting

confidence: 61%

Selecting representative benchmark inputs for exploring microprocessor design spaces

Breughe

Eeckhout

2013

TACO

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The design process of a microprocessor requires representative workloads to steer the search process toward an optimum design point for the target application domain. However, considering a broad set of workloads to cover the large space of potential workloads is infeasible given how time-consuming design space exploration typically is. Hence, it is crucial to select a small yet representative set of workloads, which leads to a shorter design cycle while yielding a (near) optimal design.Prior work has mostly looked into selecting representative benchmarks; however, limited attention was given to the selection of benchmark inputs and how this affects workload representativeness during design space exploration. Using a set of 1,000 inputs for a number of embedded benchmarks and a design space with around 1,700 design points, we find that selecting a single or three random input(s) per benchmark potentially (in a worst-case scenario) leads to a suboptimal design that is 56% and 33% off, on average, relative to the optimal design in our design space in terms of Energy-Delay Product (EDP). We then propose and evaluate a number of methods for selecting representative inputs and show that we can find the optimum design point with as few as three inputs.

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Section: Optimization Criterionsupporting

confidence: 61%

Selecting representative benchmark inputs for exploring microprocessor design spaces

Breughe

Eeckhout

2013

TACO

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“…Hill-Climbing optimizes fairness particularly well: it increases fairness by 25.0% over FLUSH and 43.3% over ICOUNT for the 2-thread-workloads. Note, however, that hill climbing policies optimize the performance metric on an interval-by-interval basis, a strategy that does not guarantee an overall optimum [17]. This also holds for the throughput and fairness metrics used in this paper which is to the disadvantage of Hill-Climbing.…”

Section: Simulation Results Analysismentioning

confidence: 94%

Managing SMT resource usage through speculative instruction window weighting

Vandierendonck

Seznec

2011

ACM Trans. Archit. Code Optim.

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Simultaneous multithreading processors dynamically share processor resources between multiple threads. In general, shared SMT resources may be managed explicitly, e.g. by dynamically setting queue occupation bounds for each thread as in the DCRA and Hill-Climbing policies. Alternatively, resources may be managed implicitly, i.e. resource usage is controlled by placing the desired instruction mix in the resources. In this case, the main resource management tool is the instruction fetch policy which must predict the behavior of each thread (branch mispredictions, long-latency loads, etc.) as it fetches instructions. In this paper, we present the use of Speculative Instruction Window Weighting (SIWW) to bridge the gap between implicit and explicit SMT fetch policies. SIWW estimates for each thread the amount of outstanding work in the processor pipeline. Fetch proceeds for the thread with the least amount of work left. SIWW policies are implicit as fetch proceeds for the thread with the least amount of work left. They are also explicit as maximum resource allocation can also be set. SIWW can use and combine virtually any of the indicators that were previously proposed for guiding the instruction fetch policy (number of in-flight instructions, number of low confidence branches, number of predicted cache misses, etc.). Therefore, SIWW is an approach to designing SMT fetch policies, rather than a particular fetch policy. Targeting fairness or throughput is often contradictory and a SMT scheduling policy often optimizes only one performance metric at the sacrifice of the other metric. Our simulations show that the SIWW fetch policy can achieve at the same time state-of-the-art throughput, state-of-the-art fairness and state-of-the-art harmonic performance mean. Key-words: Managing SMT Resource Usage through Speculative Instruction Window WeightingRésumé : Les processeurs SMT partagent les ressources du processeur dynamiquementà l'exécution entre les différents processus. Dans ce rapport, nous présentons une nouvelle politique d'allocation de ressources entre les processus qui permetà la fois un très haut débit et une distributionéquitable des ressources. Mots-clés : Multiflot excution simultanée

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“…Note that, in Fig. 10, the average EDP is computed using ðAE DelayÞ Ã ðAE EnergyÞ, as suggested in [29].…”

Section: Resultsmentioning

confidence: 99%

Submitted to IEEE Transactions on Parallel and Distributed Systems Special Issue on CMP Architectures

Gao

Dimitrov

et al. 2015

IEEE Trans. Parallel Distrib. Syst.

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Dual-core execution (DCE) is an execution paradigm proposed to utilize chip multiprocessors to improve the performance of single-threaded applications. Previous research has shown that DCE provides a complexity-effective approach to building a highly scalable instruction window and achieves significant latency-hiding capabilities. In this paper, we propose to optimize DCE for power efficiency and/or transient-fault recovery. In DCE, a program is first processed (speculatively) in the front processor and then reexecuted by the back processor. Such reexecution is the key to eliminating the centralized structures that are normally associated with very large instruction windows. In this paper, we exploit the computational redundancy in DCE to improve its reliability and its power efficiency. The main contributions include: 1) DCE-based redundancy checking for transient-fault tolerance and a complexity-effective approach to achieving full redundancy coverage and 2) novel techniques to improve the power/energy efficiency of DCE-based execution paradigms. Our experimental results demonstrate that, with the proposed simple techniques, the optimized DCE can effectively achieve transientfault tolerance or significant performance enhancement in a power/energy-efficient way. Compared to the original DCE, the optimized DCE has similar speedups (34 percent on average) over single-core processors while reducing the energy overhead from 93 percent to 31 percent.

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The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best

Cited by 15 publications

References 5 publications

Selecting representative benchmark inputs for exploring microprocessor design spaces

Selecting representative benchmark inputs for exploring microprocessor design spaces

Managing SMT resource usage through speculative instruction window weighting

Submitted to IEEE Transactions on Parallel and Distributed Systems Special Issue on CMP Architectures

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