The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits

Kaczer, B.; Franco, J.; Weckx, Pieter; Roussel, Philippe; Simicic, Marko; Putcha, Vamsi; Bury, E.; Cho, Moon Ju; Degraeve, R.; Linten, Dimitri; Groeseneken, G.; Debacker, Peter; Parvais, B.; Raghavan, Praveen; Catthoor, Francky; Rzepa, G.; Waltl, Michael; Goes, Wolfgang; Grasser, T.

doi:10.1016/j.sse.2016.07.010

Cited by 20 publications

(8 citation statements)

References 82 publications

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“…Notice that the fitting procedure reported here is appropriate for small enough FETs, i.e., devices where charge de-trapping during the recovery phase is observed as sudden changes in current. As such behavior has been described for other 65nm technologies and below (see for instance, 45nm and 65nm bulk CMOS in [22], 28nm in [23], 8nm and 7nm FinFET in [24]), it is quite reasonable to state that the work can be readily adopted for 65nm technologies and below. As for the upper limit, though this would depend on the particular technology, it could be around 100nm in width and length.…”

Section: Fitting Of Experimental Datamentioning

confidence: 77%

Determination of the Time Constant Distribution of a Defect-Centric Time-Dependent Variability Model for Sub-100-nm FETs

Saraza-Canflanca

Castro-López

Roca

et al. 2022

IEEE Trans. Electron Devices

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The origin of some Time-Dependent Variability phenomena in FET technologies has been attributed to the charge carrier trapping/de-trapping activity of individual defects present in devices. Although some models have been presented to describe these phenomena from a socalled defect-centric perspective, limited attention has been paid to the complex process that goes from the experimental data of the phenomena up to the final construction of the model and all its components, specifically the one that pertains to the time constant distribution. This paper presents a detailed strategy aimed at determining the defect time constant distribution, specifically tailored for small area devices, using data obtained from conventional characterization procedures.

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Section: Fitting Of Experimental Datamentioning

confidence: 77%

Determination of the Time Constant Distribution of a Defect-Centric Time-Dependent Variability Model for Sub-100-nm FETs

Saraza-Canflanca

Castro-López

Roca

et al. 2022

IEEE Trans. Electron Devices

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“…To describe the impact of the defects on transistors and circuits a combination of time‐zero and time‐dependent distributions of transistor parameters must be employed, [ 106 ] see Figure . The time‐zero variability of parameters such as V th or SS in circuit simulations is relatively straight forward to consider via Monte Carlo simulations.…”

Section: Performance Evaluation and Compact Modeling Of Transistorsmentioning

confidence: 99%

“…[4] The time-dependent changes, on the other hand, are largely determined by charging and discharging processes of insulator and interface defects. [94,106,108,[117][118][119][120] In initial studies on single defects in scaled MoS 2 /SiO 2 transistors, distinct charge trapping events were observed using RTN measurements, see Figure 4a,b. [40,91] RTN signals as shown in Figure 4a are characterized by discrete transitions between two disjunctive current levels which are recorded at constant applied gate and drain voltages.…”

Section: Modeling the Impact Of Defects On Transistorsmentioning

confidence: 99%

Perspective of 2D Integrated Electronic Circuits: Scientific Pipe Dream or Disruptive Technology?

et al. 2022

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Within the last decade, considerable efforts have been devoted to fabricating transistors utilizing 2D semiconductors. Also, small circuits consisting of a few transistors have been demonstrated, including inverters, ring oscillators, and static random access memory cells. However, for industrial applications, both time‐zero and time‐dependent variability in the performance of the transistors appear critical. While time‐zero variability is primarily related to immature processing, time‐dependent drifts are dominated by charge trapping at defects located at the channel/insulator interface and in the insulator itself, which can substantially degrade the stability of circuits. At the current state of the art, 2D transistors typically exhibit a few orders of magnitude higher trap densities than silicon devices, which considerably increases their time‐dependent variability, resulting in stability and yield issues. Here, the stability of currently available 2D electronics is carefully evaluated using circuit simulations to determine the impact of transistor‐related issues on the overall circuit performance. The results suggest that while the performance parameters of transistors based on certain material combinations are already getting close to being competitive with Si technologies, a reduction in variability and defect densities is required. Overall, the criteria for parameter variability serve as guidance for evaluating the future development of 2D technologies.

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“…2,[4][5][6][7] Several key advantages can be expected from downscaling FET molecular sensors. First, from the scaling of metal-oxide-semiconductor FETs (MOSFET) with a surface area A, it is known that the threshold shift associated with single oxide defects scales as ∼1/A, 8,9 while the FET noise scales as $ 1= ffiffiffi A p . 10,11 Also, for electrolyte-gated nanoscale FETs it is pointed out that single oxide charges can become detectable.…”

Section: Introductionmentioning

confidence: 99%

Unraveling the impact of nano-scaling on silicon field-effect transistors for the detection of single-molecules

et al. 2023

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The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits

Cited by 20 publications

References 82 publications

Determination of the Time Constant Distribution of a Defect-Centric Time-Dependent Variability Model for Sub-100-nm FETs

Determination of the Time Constant Distribution of a Defect-Centric Time-Dependent Variability Model for Sub-100-nm FETs

Perspective of 2D Integrated Electronic Circuits: Scientific Pipe Dream or Disruptive Technology?

Unraveling the impact of nano-scaling on silicon field-effect transistors for the detection of single-molecules

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