The Design, Analysis, and Development of Highly Manufacturable 6-T SRAM Bitcells for SoC Applications

Venkatraman, R.; Castagnetti, R.; Kobozeva, O.; Duan, Franklin Li; Kamath, Arvind; Sabbagh, S.T.; Vilchis-Cruz, M.A.; Liaw, J.J.; You, Jyh-Cheng; Ramesh, S.

doi:10.1109/ted.2004.841346

Cited by 19 publications

(6 citation statements)

References 5 publications

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“…3, is smaller than the area of two one-cell primitive cells because it was designed to increase the integration level by sharing the n-well used for PMOS transistors [14]. As described in Section III, the TCP value of the SRAM was around 47 and 21 fF at 180 and 65 nm, respectively.…”

Section: A Simulations Of Test Methods With Nvsmentioning

confidence: 99%

“…The layout of the cells was tightly spaced to minimally satisfy the design rules in every portion of the cell layout spaces. Two-bit cells were designed as a single primitive element to share the n-well and supply voltage (VDD) to increase the density [14]. The shared portion is shown in the dotted box in Fig.…”

Section: A Layout-based Coupling Capacitor With Defect Considerationsmentioning

confidence: 99%

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Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress

Bae

Baeg

Park

2012

IEEE Trans. Instrum. Meas.

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The physical distance between adjacent memory cells is rapidly decreasing as memory density increases and technology geometry shrinks. As a result of the narrower distance, the capacitance between adjacent cells, which are referred to as the cell coupling capacitor (C CCP ), increases and behaves as the source of crosstalk. The crosstalk is further aggravated by increasing operational speeds. When the sizes of the C CCP are marginal, they may not be detected by normal test patterns but can appear when various stresses accumulate. When they are not detected in an early manufacturing stage, they become the source of intermittent failures. Creating a complex test environment is sometimes rejected at the expense of higher parts per million of a device. In this paper, a negative voltage stress is applied to bit lines to test and diagnose the issues from the marginal C CCP . The negative voltage level is closely correlated to the C CCP size, which implies that the proposed method can be used as a vehicle to diagnose the potential issues due to cell coupling capacitors. The simulation results demonstrated that the negative stress voltage can screen the cell coupling capacitors from a few femtofarads to tens of femtofarads in an experimental circuit. The proposed technique has been validated by test chip using 130-nm technology.Index Terms-Bit line, capacitive defect, cell coupling capacitor (C CCP ), crosstalk, memory, negative voltage stress (NVS).

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Section: A Simulations Of Test Methods With Nvsmentioning

confidence: 99%

Section: A Layout-based Coupling Capacitor With Defect Considerationsmentioning

confidence: 99%

Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress

Bae

Baeg

Park

2012

IEEE Trans. Instrum. Meas.

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“…The 0.13 μm platform was the first in which two bit-cells were used by foundries for high volume manufacturing: 2.43 μm 2 , that is a direct shrink from 0.18 μm, and 2.14 μm 2 , for high-density low-leakage application. Down to 80 nm, a 6-T (six transistors) SRAM Bit cell of type A to D was used [40]. The 65 nm foundry technology [41], introduced a new layout configuration, that did not have any AA or Poly corners that could be rounded as explained above.…”

Section: Low Power Consideration For Srammentioning

confidence: 99%

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Shauly

2012

JLPEA

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Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. However, the drawbacks of these solutions, in terms of greater manufacturing complexity (and higher cost) and speed degradation, call for “optimized” solutions. This paper reviews the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors. For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. Finally, different techniques for leakage and power reduction at the circuit level are discussed

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“…The susceptible area, A, for the SRAM cell within the TCAM was measured off a layout [12], and for the new feedback-enhanced TCAM cells the increase in the value of A was projected from the same layout. QSp and QSn for a 70nm process was extrapolated from the trends found in [8] and the critical charge, Qcrit for each node, was found through an HSPICE simulation [7] by injecting charge with a piece-wise linear current waveform in the shape shown in [13].…”

Section: Figure 8: Reduction In the Ser Of The Different Cross-couplementioning

confidence: 99%

A family of cells to reduce the soft-error-rate in ternary-CAM

Azizi

Najm

2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These events, also referred to as single-event upsets (SEUs), will become more problematic in future technologies. This paper presents a ternary content-addressable memory (CAM) design with high immunity to SEU. Conventionally, errorcorrecting codes (ECC) have been used in SRAMs to address this issue, but these techniques are not immediately applicable to CAMs because they depend on processing the full contents of the memory word outside the array, which is not possible in a normal CAM access. We propose a family of TCAM cells that reduce the SER at the cost of some area increase. An SER reduction of up to 40% can be obtained with a 18% increase of area; another design reduces the SER by 16% with only a 5% increase in area.

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The Design, Analysis, and Development of Highly Manufacturable 6-T SRAM Bitcells for SoC Applications

Cited by 19 publications

References 5 publications

Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress

Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

A family of cells to reduce the soft-error-rate in ternary-CAM

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