1992
DOI: 10.1109/72.129409
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The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

Abstract: A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex s… Show more

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Cited by 31 publications
(7 citation statements)
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“…Several examples of VLSI WTA networks of spiking neurons can be found in the literature [2,15,24,37,40,51]. In 1992, De Yong et al [24] proposed a VLSI WTA spiking network consisting of four neurons.…”
Section: Soft Winner-take-all Circuitsmentioning
confidence: 99%
See 1 more Smart Citation
“…Several examples of VLSI WTA networks of spiking neurons can be found in the literature [2,15,24,37,40,51]. In 1992, De Yong et al [24] proposed a VLSI WTA spiking network consisting of four neurons.…”
Section: Soft Winner-take-all Circuitsmentioning
confidence: 99%
“…In 1992, De Yong et al [24] proposed a VLSI WTA spiking network consisting of four neurons. The authors implemented the WTA mechanism through all-to-all inhibitory connections.…”
Section: Soft Winner-take-all Circuitsmentioning
confidence: 99%
“…Therefore, the development of highly scalable and low-power electronic synapse that can mimic the synaptic functions of a biological synapse is important for the development of a versatile, large-scale neuromorphic system. Various efforts have been devoted to developing the electronic synapse by exploiting very-large-scale integrated (VLSI) analog complementary metal-oxide-semiconductor (CMOS) circuit, mixed analog/digital circuit, and CMOS-based application specific integrated circuit (ASIC). These approaches require multiple transistors to realize one electronic synapse, thus resulting in large chip area and high power consumption. Therefore, the attractive features of emerging nanoelectronic devices have started to gain attention for resolving the challenges of CMOS-based approaches.…”
Section: Flexible Pv3d3 Memristor For Electronic Synapsementioning
confidence: 99%
“…Typically hybrid implementations use analog neurons taking advantage of their smaller size and lower power consumption and use digital memories for permanent weight storage [85,86]. The mixed-signal design of the analog neurons with the digital memories on the same die introduces a lot of noise problems and requires isolation of the sensitive analog parts from the noisy digital parts using techniques such as guard rings.…”
Section: Hybrid Neural Hardware Implementationsmentioning
confidence: 99%