The design of a new FPGA architecture

Stansfield, Tony; Page, Ian

doi:10.1007/3-540-60294-1_93

Cited by 11 publications

(7 citation statements)

References 1 publication

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“…As illustrated in [8], a PLA representation is good for complex inter-related function while LUT based representation as in traditional FPGAs is suitable for small complex gates. Such a scenario is often encountered for circuits that require many "XOR"-like logic function leading to exponentially large number of product terms in the PLA representation.…”

Section: A Hybrid Cam-lut Approachmentioning

confidence: 99%

“…Although, efforts [8,13] have been made to configure a small storage at each CLB (in a conventional SRAM-based FPGA) both as a CAM and a LUT for efficient functional representation, the limited number of inputs to a CLB fail to exploit the high integration density offered by modern CAM designs. For efficient utilization of the die real estate, it is therefore desirable to have a large content addressable storage, which can be configured as multi input-output PLAs.…”

Section: Introductionmentioning

confidence: 99%

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Reconfigurable computing using content addressable memory for improved performance and resource usage

Sauseng

Bhunia

2008

Proceedings of the 45th Annual Design Automation Conference

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Conventional FPGA architectures leverage on the spatial computing model where the design to be realized is represented in the form of multi-input single-output lookup tables (LUTs). However, such a model incorporates a reconfigurable interconnect network which leads to significant design overhead and poor scalability with process technology. In this paper, we propose a multi-cycle Memory Based Computational methodology that utilizes Content Addressable Memory (CAM) as the underlying reconfigurable fabric. The use of CAM in the proposed framework leads to significant reduction in memory requirement compared to LUT-based approach. Simulation results for standard benchmark circuits indicate that the proposed CAM based implementation improves the memory requirement significantly compared to its LUT counterpart, at the cost of little or no degradation in performance.

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Section: A Hybrid Cam-lut Approachmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Reconfigurable computing using content addressable memory for improved performance and resource usage

Sauseng

Bhunia

2008

Proceedings of the 45th Annual Design Automation Conference

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“…The Xilinx XC6200 series [4] and the National Semiconductor CLAY [5] series use a random access method for reconfiguration. The configuration cells for these devices can be accessed in a similar way as cells in a standard RAM.…”

Section: Pathlconfiiation Headermentioning

confidence: 99%

Wormhole run-time reconfiguration

Bittner

Athanas

1997

Proceedings of the 1997 ACM Fifth International Symposium on Field-Programmable Gate Arrays - FPGA '97

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Configurable Computing Machines (CCMs) are an emerging class of computing platform which provide the computational performance benefits of ASICs, yet retain the flexibility and rapid recontigurability of general purpose microprocessors. In these platforms, computational "hardware" is essentially swapped in and out of the platform as needed, much like paging in virtual memory systems. For an efficient platform, the swapping of the computational hardware (referred to as Run-Time Reconfiguration, or RTR) must be rapid. Thus far, the means of altering the configuration of CCMs has relied on global control strategies that present a fundamental bottleneck to the potential bandwidth of configuration information flowing into the CCM. Wormhole Run-time Reconfiguration is presented as a distributed control methodology that is applicable not only to the problem of device-level CCM reconfiguration, but to system-wide concurrent computing as a whole. The Virginia Tech Colt/Stallion integrated circuits are computational FPGAs incorporating Wormhole RTR concepts, and are discussed as a case study.

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“…The work described the development of the FPGA and looked at the mapping onto it of some interesting application circuit elements. The design was discussed in approximately chronological order which allows explaining other options considered and rejected during the development process [5].…”

Section: Introductionmentioning

confidence: 99%

Successfully Designing FPGA-Card for Mobile Robot Research

Naji¹,

Abbes²,

Abdelmoula³

et al. 2016

IJCA

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This paper describes a new design of electronic board based on FPGA Cyclone III. The main objective of this idea is towards small size, fast Real Time processing, high integration and analog peripherals that are not disposal in available FPGA development kits. For the optimum performance a Microcontroller 8 Bits Flash CMS was used which is interfaced with FPGA and used as an ADC to make all the data processing on board in Real Time. This card can be used in many applications on the field of mobile robotics like autonomous navigation and intelligent parallel parking. To communicate and supervise all activities of mobile robots, an RF module was installed on the board which serves as a transmitter to a host computer that will receive all information in Real Time. The paper introduces many challenging issues which are being addressed to enhance in laboratories researchers project planning, designing and implementing capabilities. These issues are the FPGA performance, interfacing the microcontroller to the FPGA, implementing the flexible processing algorithms and high speed interconnection between the boards. The developed card was tested via the implementation of real time algorithms, and was validated experimentally on a mobile robot system.

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The design of a new FPGA architecture

Cited by 11 publications

References 1 publication

Reconfigurable computing using content addressable memory for improved performance and resource usage

Reconfigurable computing using content addressable memory for improved performance and resource usage

Wormhole run-time reconfiguration

Successfully Designing FPGA-Card for Mobile Robot Research

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