The design of an asynchronous TinyRISC/sup TM/ TR4101 microprocessor core

Christensen, K.T.; Jensen, P.; Korger, P.; Sparsø, Jens

doi:10.1109/async.1998.666498

Cited by 20 publications

(6 citation statements)

References 7 publications

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“…The routers and links are designed by asynchronous circuits, where request-acknowledge based handshaking is operated, while the processing cores are designed by synchronous circuits. The asynchronous circuits are classified into a bundled-data style [3], and the QDI logic style [4]- [6]. Since the QDI logic style avoids any timing constraints with an only assumption, where the wires at fanout point must have roughly equal delay, robust asynchronous circuits can be implemented under variations, such as process and voltage variations, while the bundled-data style requires timing margins, such as the synchronous circuits.…”

Section: A Global Asynchronous Communication In Gals-noc Architecturementioning

confidence: 99%

High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip

Onizawa

Hanyu

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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This paper presents a high-throughput asynchronous protocol converter between two-phase communication links and four-phase pipelined routers for asynchronous Network-on-Chip. In the proposed protocol converter, two-phase input and output signals are encoded to and decoded from the four-phase signals, respectively, by using two controllers which are attached to the router. Since the two controls are realized respectively by using only the input signal and the output signal, the "twoto-four-phase" and "four-to-two-phase" conversions are independently performed. Therefore, each conversion is completely performed without input-output dependency. As a result, the proposed protocol converter achieves an up to 77 % increase in throughput under a comparable energy consumption with respect to that of a conventional protocol converter on a Silterra 0.13-m CMOS technology.

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Section: A Global Asynchronous Communication In Gals-noc Architecturementioning

confidence: 99%

High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip

Onizawa

Hanyu

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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“…Asynchronous VLSI design has been gaining a new popularity since the end of the 80's. Representative results in asynchronous microprocessor design have been achieved [6,7,8,9,10,11,14,15]. Most designs address high performance with reduced power consumption, and utilize specialized techniques which involve layout topology and physical delay assumptions.…”

Section: Introductionmentioning

confidence: 98%

Delay-insensitive synthesis of the MCS 251 microcontroller core for low power applications

Gloria

Olivieri²,

Palma³

1999

Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium

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We present the design of an asynchronous microcontroller core featuring binary compatibility with the MCS 251 family. The work is involved in a specific application project targeting portable electromagnetic measurement systems with very low power consumption. Delay insensitivity was chosen to allow a fast design of complex but safe asynchronous circuits, by automatic synthesis and independency of layout topology. On the other hand, unconventional logic cells must be employed, and special features have been introduced in the synthesis tool to dominate the circuit area, estimating the power consumption and interfacing with more conventional CAD flows. A preliminary set of results is illustrated in detail.

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“…Unlike the clockless stochastic decoder, the hardware implementation of the asynchronous circuits have been presented [25]- [27]. A wire-delay dependent (WDD) scheduling algorithm is the extension of the WDI scheduling algorithm in order to lower the error floors.…”

Section: Wdd Schedulingmentioning

confidence: 99%

Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model

Onizawa

Gross

Hanyu

et al. 2014

IEICE Trans. Inf. & Syst.

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SUMMARYStochastic decoding provides ultra-low-complexity hardware for high-throughput parallel low-density parity-check (LDPC) decoders. Asynchronous stochastic decoding was proposed to demonstrate the possibility of low power dissipation and high throughput in stochastic decoders, but decoding might stop before convergence due to "lock-up", causing error floors that also occur in synchronous stochastic decoding. In this paper, we introduce a wire-delay dependent (WDD) scheduling algorithm for asynchronous stochastic decoding in order to reduce the error floors. Instead of assigning the same delay to all computation nodes in the previous work, different computation delay is assigned to each computation node depending on its wire length. The variation of update timing increases switching activities to decrease the possibility of the "lock-up", lowering the error floors. In addition, the WDD scheduling algorithm is simplified for the hardware implementation in order to eliminate time-averaging and multiplication functions used in the original WDD scheduling algorithm. BER performance using a regular (1024, 512) (3,6) LDPC code is simulated based on our timing model that has computation and wire delay estimated under ASPLA 90nm CMOS technology. It is demonstrated that the proposed asynchronous decoder achieves a 6.4-9.8× smaller latency than that of the synchronous decoder with a 0.25-0.3 dB coding gain.

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The design of an asynchronous TinyRISC/sup TM/ TR4101 microprocessor core

Cited by 20 publications

References 7 publications

High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip

High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip

Delay-insensitive synthesis of the MCS 251 microcontroller core for low power applications

Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model

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