The design of log-domain filters based on the operational simulation of LC ladders

Perry, David J.; Roberts, G.W.

doi:10.1109/82.544029

Cited by 121 publications

(65 citation statements)

References 22 publications

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“…3 with the components drawn in thick wires in 6. Second, as was proposed in [8] and done in [7] for a damped integrator, a large portion of the circuitry can be replaced by simple current sources, as shown in the lower half of Fig. 6.…”

Section: The Input and Output Interface Circuitrymentioning

confidence: 99%

“…The resulting transfer function is described by equation (8) at the bottom of the page, where I 1 and I 2 are the bias currents of cells FF1 and FF2 respectively, and I o is the bias current of the remaining cells of the filter. Equation (8) shows that the system in Fig. 1 is linear, with two asymmetric zeros, tunable through I 1 and I 2 .…”

Section: Filter Structure and Specificationsmentioning

confidence: 99%

“…Higher order filters can be synthesized using a state-space based approach [13], or the less component-sensitive LC-ladder based approach [8], as long as the transfer function of the log-domain integrator used has a general format similar to (3).…”

Section: (A)mentioning

confidence: 99%

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A low-power, 5-70MHz, 7th-order filter with programmable boost, group delay, and gain using instantaneous companding

Baki

El-Gamal

2001

Proceedings of the 2001 International Symposium on Low Power Electronics and Design - ISLPED '01

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A seventh-order 0.05 o equiripple linear-phase continuous-time filter employing, for the first time, instantaneous companding, was designed and integrated in a mature bipolar process. The amount of boost (up to 13dB) and group-delay adjustment (30%) are digitally programmable. The DC gain is controllable up to 10dB, and the -3dB frequency (f c ) is tunable from 5 to 70MHz. The output swing for 1% THD is higher than 100mV pp , with a 1.5V supply. The filter consumes very low power (5-13mW for f c = 70MHz) compared to conventional implementations (e.g. 120mW for f c = 100MHz [1]). INTRODUCTIONThe continuous decrease of the supply voltages of modern integrated circuit technologies often necessitates an increase in the power consumption of conventional analog circuit processors, in order to maintain the same Dynamic Range (DR) and chip area for a given bandwidth [2]. To mitigate this restriction, the use of companding-based signal processors was proposed [3]- [4]. The last ten years have seen a growing interest in employing companding for continuous-time filtering. This was paralleled by the design and fabrication of several integrated log-domain filter circuits in a variety of technologies (e.g.[5]- [11]). These implementations were mostly low-order filters for proof of concept and / or performance exploration; they did not target particular applications or specifications. In order to gain industrial acceptance, the performance of companding-based filters needs to match, if not exceed, the performance of conventional filtering schemes, and should be evaluated in the context of concrete applications. Recently, a micropower log-domain filter for the Digital European Cordless Telephone (DECT) standard was reported [10]. Hard-disk-drive (HDD) read channels is another application where the requirements on filtering is constantly on the rise in terms of power consumption, tunability, speed, and robustness [12]. The objective of the work presented in this paper is to design a companding-based prefilter for HDD applications which exceeds state-of-the-art bipolar/BiCMOS designs in terms of voltage supply and power consumption (5mW without boost and equalization for f c = 70MHz versus 120mW for f c = 100MHz in [1]), while satisfying the requirements of partial response maximum likelihood (PRML) read channel front-ends. In servo mode, the filter has a cutoff frequency as low as 5MHz and dissipates less than 500µW. Figure 1 shows the overall structure of the 7 th -order filter presented in this paper, along with a summary of the system specifications (details in Section 5). The input signal is compressed before being processed, which ensures signal integrity over a large range of signal levels. At the output, the signal is expanded to restore its DR. When the compression / uncompression are logarithmic / exponential, the resulting filter is known as a "log-domain filter" [13]. CONCEPT OF LOG-DOMAIN FILTERINGThe concept of log-domain filtering is illustrated in Fig. 2 (a) for a simple first-order filter. The input signal v IN ,...

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Section: The Input and Output Interface Circuitrymentioning

confidence: 99%

Section: Filter Structure and Specificationsmentioning

confidence: 99%

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A low-power, 5-70MHz, 7th-order filter with programmable boost, group delay, and gain using instantaneous companding

Baki

El-Gamal

2001

Proceedings of the 2001 International Symposium on Low Power Electronics and Design - ISLPED '01

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“…While these values would appear to overestimate of the performance of these lateral PNP devices, it will be demonstrated in Chapter 3 and 4 that log-domain filter circuits which make use these devices can operate at frequencies at over 10 MHz. It has previously been shown that log-domain filters can be made to operate up to frequencies of approximately 1/10 of the fT of the slowest transistors [5]. If this were the case in this work as weIl, it would suggest that the effective fT of the lateral PNP transistors would be on the order of 100 MHz or higher, weIl within a factor of ten of the effective fT values above from simulation.…”

Section: (A) This Capacitance Does Not Fit Inmentioning

confidence: 48%

“…proposed by Perry and Roberts [4], [5] in 1995. The method introduced signal-ftow graphs as a means to describe the operation of the filter, from which common filter design techniques, such as the operational simulation of LC ladders [6], could be applied.…”

Section: -_mentioning

confidence: 99%

The development of bipolar log domain filters in a standard CMOS process

Duerden

Roberts²,

Deen³

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

The design of log-domain filters based on the operational simulation of LC ladders

Cited by 121 publications

References 22 publications

A low-power, 5-70MHz, 7th-order filter with programmable boost, group delay, and gain using instantaneous companding

A low-power, 5-70MHz, 7th-order filter with programmable boost, group delay, and gain using instantaneous companding

The development of bipolar log domain filters in a standard CMOS process

Synthesis of Static and Dynamic Translinear Circuits

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