The design of nectar: a network backplane for heterogeneous multicomputers

Abstract

Nectar is a "network backplane" for use in heterogeneous multicomputers. The initial system consists of a starshaped fiber-optic network with an aggregate bandwidth of 1.6 gigabits/second and a switching latency of 700 nanoseconds. The system can be scaled up by connecting hundreds of these networks together.The Nectar architecture provides a flexible way to handle heterogeneity and task-level parallelism. A wide variety of machines can be connected as Nectar nodes and the Nectar system software allows applications to communicate at a high level. Protocol processing is off-loaded to powerful communication processors so that nodes do not have to support a suite of network protocols.We have designed and built a prototype Nectar system that has been operational since November 1988. This paper presents the motivation and goals for Nectar and describes its hardware and software. The presentation emphasizes how the goals influenced the design decisions and led to the novel aspects of Nectar.

Partitioning tasks between a pair of interconnected heterogeneous processors: A case study

“…Such networks of heterogeneous computers [4,5] may be able to produce a total execution time that is shorter than the execution time that can be obtained by running the entire program on any single machine. Other studies [6][7][8] have attempted to show that networks of heterogeneous machines can be more cost-effective than a single large machine while producing the same (or higher) performance.…”

A configurable network protocol for cluster based communications using modular hardware primitives on an intelligent NIC

“…A similar approach to ours has been studied extensively over Like our proposal, the nectar system [1] has identified the importance of moving protocol processing across the system bus and into the network interface. However, nectar is implemented with ASICs which are fixed hardware circuits.…”

“…The packet interface provides the starting address of data, length of the data, and the destination node for the 1 Rate control has not been implemented yet data. The ack interface provides both the base packet number being acknowledged and a bit pattern indicating the packets beyond that base that have been received.…”

“…Some modern high-performance network interfaces provide these protocol processing features as well as some other non-trivial computing capabilities [3,15,1,16]. For example, Myrinet provides a LANai processor ranging up to 200MHz [3] and even commodity network cards, like those using the Alteon Tigon chipsets, have begun to add embedded processors [17].…”

“…In [4], the authors show that implementing non trivial network operations like collective communications on such hardware improves the performance significantly. Unlike other efforts where the sequential embedded processor limits protocol processing performance [17,18,1], the INIC distinguishes itself by providing abundant computing power and allowing the remaining reconfigurable resources to be used for computation.…”