The design of radiation-hardened ICs for space: a compendium of approaches

Kerns, S.E.; Shafer, B.D.; Rockett, Leonard R.; Pridmore, J.S.; Berndt, D.F.; Vonno, Nicolaas Van; Barber, Frank E.

doi:10.1109/5.90115

Cited by 75 publications

(24 citation statements)

References 66 publications

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“…The approaches to increasing system reliability to SEUs and soft errors can be divided into techniques based on fault avoidance (intolerance) and fault detection/tolerance. Radiation hardening techniques for fault avoidance to increase reliability primarily rely on conservative design practices such as the use of high-reliability components, the exclusion of radiation-sensitive circuit styles (such as dynamic logic and non-complementary metal-oxide semiconductor (non-CMOS) styles) and the incorporation of sufficient functional margin in circuit designs to account for anticipated shifts in circuit characteristics [7], [19], [34]. Fault detection/tolerance techniques are used when fault avoidance alone cannot economically be used to meet reliability requirements during design.…”

Section: Introductionmentioning

confidence: 99%

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Gate sizing to radiation harden combinational logic

Zhou

Mohanram

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

281

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Abstract-A gate-level radiation hardening technique for costeffective reduction of the soft error failure rate in combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates that have the lowest logical masking probability to achieve costeffective tradeoffs between overhead and soft error failure rate reduction. The asymmetry in the logical masking probabilities at a gate is leveraged by decoupling the physical from the logical (Boolean) aspects of soft error susceptibility of the gate. Gates are hardened to single-event upsets (SEUs) with specified worst case characteristics in increasing order of their logical masking probability, thereby maximizing the reduction in the soft error failure rate for specified overhead costs (area, power, and delay). Gate sizing for radiation hardening uses a novel gate (transistor) sizing technique that is both efficient and accurate. A full set of experimental results for process technologies ranging from 180 to 70 nm demonstrates the cost-effective tradeoffs that can be achieved. On average, the proposed technique has a radiation hardening overhead of 38.3%, 27.1%, and 3.8% in area, power, and delay for worst case SEUs across the four process technologies.

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Section: Introductionmentioning

confidence: 99%

“…Note that a detailed discussion of these techniques is beyond the scope of this paper. The references in this section are representative and by no means exhaustive; the reader is referred to [7], [19], [23], and [42] for an exhaustive introduction and survey of this area.…”

Section: Introductionmentioning

confidence: 99%

Gate sizing to radiation harden combinational logic

Zhou

Mohanram

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

281

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“…a Single Event Upset (SEU), in computer memory or combinational logic circuits. SEU effects are found at sea level [24,31], in airborne avionics [19,20], and in space [1,2,5,7,10,12,14,23,24,25,26,27,28,32]. The effect of SEUs on chips has been extensively investigated and programs, e.g.…”

Section: Introductionmentioning

confidence: 99%

“…Radiation hardening techniques typically involve integrated circuit process changes. Shielding, a fault-avoidance technique may be counter productive due to bremsstrahlung radiation and nonlinear energy deposition rates [14]. Fault-tolerance techniques include the use of ECCs for memories and processor registers; replication with voting for ALUs and processors; and watchdogs, checkpoint-rollback, and memory reloading for software execution.…”

Section: Seu Controlmentioning

confidence: 99%

System effects of single event upsets

Finn¹

1989

7th Computers in Aerospace Conference

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At the system level, SEUs in processors are controlled by fault-tolerance techniques such as replication and voting, watchdog processors, and tagged data schemes [13,16,30]. SEUs in memory subsystems are controlled by use of error control codes (ECCs) [4,17,21] and a process called scrubbing. The scrubbing process periodically reads each word in the memory. If the number of faulty digits in a word is less than or equal to the number the ECC can correct, then the digits are corrected and the word is written back to memory. If the number of faulty digits exceeds the ECC's capability, the errors cannot be corrected and the memory has failed. Fault-tolerance to memory failures requires either physical redundancy via replication or temporal redundancy via checkpoint rollback schemes. In most aerospace applications physical redundancy is undesirable because mass, volume, and power are at a premium.The rate at which SEUs are scrubbed from memory affects the performance and reliability of the entire computer system. Infrequent scrubbing leads to an accumulation of faults and increases the probability of exceeding the ECC's capability. Conversely, frequent scrubbing uses memory cycles that might otherwise be used by the operating system or an application program.There is a recognized tradeoff between using ECCs and scrubbing or using lower density, higher power, radiation-hardened semiconductors to achieve reliability [7,32]. Previous analyses of the tradeoffs between the use of simple ECCs, the additional hardware for the ECC, failure due to that additional hardware, and the system impact have been based on simplified analytical models; detailed analytical models are intractable.This paper introduces the idea of Markov modeling for SEU effects. Markov modeling allows extrapolation of chip failure rates to the subsystem and system level, allows more sophisticated tradeoff evaluations, and permits sensitivity analyses. The remainder of this paper is organized in three parts. Section 2 provides background about the SEU problem, expected SEU failure rates, and SEU control techniques. Section 3 introduces the use of Markov modeling techniques for memory subsystems and develops one model in detail. Section 4 presents the modeling results and generalizes the applicability of the modeling techniques.Single Event Upsets (SEUs) pose a serious threat to computer reliability and longevity. SEU effects are found at sea level, in airborne avionics, and in space. At the system level, SEUs in processors are controlled by replication and voting, watchdog processors, and tagged data schemes. SEUs in memory subsystems are controlled by periodically scrubbing words protected by an Error Control Code (ECC). The rate of memory scrubbing affects the performance and reliability of the entire computer system. There are tradeoffs between using radiation hardened semiconductors, scrubbing rates, and ECC capabilities. Previous tradeoff analyses have used simplified analytic models.The system effects of SEUs may be evaluated by Markov model...

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“…5). This evolution is easily explained by means of the appearance of leakage currents, already described in different irradiated CMOS devices [5]. Fig.…”

Section: Resultsmentioning

confidence: 99%