The development of a fast iterative algorithm structure of cosine transform

Gryga, Volodymyr; Kolosov, Igor V.; Danyluk, Olga

doi:10.1109/tcset.2016.7452100

Cited by 3 publications

(3 citation statements)

References 2 publications

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“…The object of our study is the process of designing multi-cycle operational sorting devices using the methodology of space-time graphs [13][14][15].…”

Section: The Study Materials and Methodsmentioning

confidence: 99%

“…To implement various types of multi-cycle operating devices (MODs) for sorting by the method of «even-odd» permutation, it is necessary to transform AFG into the corresponding space-time graphs that correspond to various types of such MODs [8,[14][15][16].…”

Section: Research Of Multicycle Operating Sorting Devicesmentioning

confidence: 99%

“…The task set is solved by applying the methodology of space-time graphs (STG) [13,14], which allows obtaining different types of structures of multi-cycle operating sorting devices [15,16]. The evaluation of the system characteristics of the resulting hardware structures will allow the designer to choose the optimal structure relative to the given technical parameters to solve the necessary problem.…”

Section: Introductionmentioning

confidence: 99%

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Design of various operating devices for sorting binary data

Hryha,

Dzundza,

Melnychuk

et al. 2023

EEJET

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The object of research is the process of designing hardware devices for sorting arrays of binary data using the methodology of space-time graphs. The main task that is solved in the work is the development and research of multi-cycle operating devices for sorting binary data in order to choose the optimal structure with predetermined technical characteristics for solving the sorting problem. As an example, the development of different types of structures of multi-cycle operating sorting devices by the method of «even-odd» permutation is shown and their system characteristics are determined. New structures of multi-cycle operating devices have been designed for a given sorting algorithm, and analytical expressions for calculating equipment costs and their performance have been given. A comparative analysis of the hardware and time complexity of the developed structures of devices for sorting binary numbers of various types with known implementations of algorithmic and pipeline operating devices was carried out. As a result, the proposed structures, when sorting large arrays of binary data (N>128), have an order of magnitude less hardware complexity due to sequential execution of the same type of operations. The time complexity of multi-cycle operating devices of combined and sequential types with large values of input data is 2.3 and 3.4 times less than that of known pipeline operating devices. A feature of the research results is the possibility of finding the optimal ratio between the hardware and time characteristics of the resulting structures of sorting devices. Owing to this, the designer will be able to choose the necessary type of device for the implementation of the corresponding task with optimal system characteristics. The field of application of the designed sorting devices is the tasks of digital processing of signals and images. The practical use of the developed sorting devices can be carried out in the form of their synthesis on software integrated logic circuits

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“…The object of our study is the process of designing multi-cycle operational sorting devices using the methodology of space-time graphs [13][14][15].…”

Section: The Study Materials and Methodsmentioning

confidence: 99%

Section: Research Of Multicycle Operating Sorting Devicesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design of various operating devices for sorting binary data

Hryha,

Dzundza,

Melnychuk

et al. 2023

EEJET

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Research and implementation of hardware algorithms for multiplying binary numbers

Gryga

Dzundza

Dadiak

et al. 2018

2018 14th International Conference on Advanced Trends in Radioelecrtronics, Telecommunications and Computer Engineering (TCSET)

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Implementation of Braun Multiplier with Efficient Pyramidal Adder Structure for Arithmetic Applications

Thokala¹

2022

IJARSCT

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Multiplier plays key role in Signal Processing and VLSI based environment applications, as it consumes more power and area compared other devices. In real time applications power and area are important parameters. Multiplier is essential component as it occupies large area and consumes more power compared to any other element .we have so many adders to design multiplier .In this paper Pyramidal adders are used which uses half-adder and full-adder to increase the speed and to reduce the number of gates used in the multiplier, but delay is not decreased significantly. If we modify the Pyramidal adder with XNOR’s and MUX instead of normal half-adder and full-adder, such pyramidal adder uses less gates and delay is reduced compared normal 16-bit adder. The use of XNOR’s and MUX in Pyramidal adder reduces delay, as the MUX function is only select the output among inputs. The use of such pyramidal adder in multiplier delay can be decreased greatly.

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The development of a fast iterative algorithm structure of cosine transform

Cited by 3 publications

References 2 publications

Design of various operating devices for sorting binary data

Design of various operating devices for sorting binary data

Research and implementation of hardware algorithms for multiplying binary numbers

Implementation of Braun Multiplier with Efficient Pyramidal Adder Structure for Arithmetic Applications

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