The development of the MU5 computer system

Capon, P. C.

doi:10.1145/359327.359333

Cited by 28 publications

(7 citation statements)

References 7 publications

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“…[15,18,25]), in a cache organization similar in spirit to that used on the MU5 (where on-processor addresses were virtual, with translation to real addresses via "current page registers" in a Store Access Control Unit [19]). We may view each L2 tag <tid, L2, L1> as the address of a virtual texture block that must be mapped to a physical texture block within L2 cache memory.…”

Section: L2 Cache Organizationmentioning

confidence: 99%

Multi-level texture caching for 3D graphics hardware

CoxMichael¹,

BhandariNarendra²,

ShantzMichael³

1998

SIGARCH Comput. Archit. News

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Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval of texture during rasterization, and the application is responsible for managing this memory. The push architecture has a bandwidth advantage, but disadvantages of limited texture capacity, escalation of accelerator memory requirements (and therefore cost), and poor memory utilization. The push architecture also requires the programmer to solve the binpacking problem of managing accelerator memory each frame. More recently graphics hardware on PC-class machines has moved to an implementation of what we call the pull architecture.Texture is stored in system memory and downloaded by the accelerator as needed. The pull architecture has advantages of texture capacity, stems the escalation of accelerator memory requirements, and has good memory utilization. It also frees the programmer from accelerator texture memory management. However, the pull architecture suffers escalating requirements for bandwidth from main memory to the accelerator. In this paper we propose multi-level texture caching to provide the accelerator with the bandwidth advantages of the push architecture combined with the capacity advantages of the pull architecture. We have studied the feasibility of 2-level caching and found the following: (1) significant re-use of texture between frames; (2) L2 caching requires significantly less memory than the push architecture; (3) L2 caching requires significantly less bandwidth from host memory than the pull architecture; (4) L2 caching enables implementation of smaller L1 caches that would otherwise bandwidth-limit accelerators on the workloads in this paper. Results suggest that an L2 cache achieves the original advantage of the pull architecturestemming the growth of local texture memory -while at the same time stemming the current explosion in demand for texture bandwidth between host memory and the accelerator.

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Section: L2 Cache Organizationmentioning

confidence: 99%

Multi-level texture caching for 3D graphics hardware

CoxMichael¹,

BhandariNarendra²,

ShantzMichael³

1998

SIGARCH Comput. Archit. News

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“…of operands in store are generated from one of 13 base address registers (BA [3][4][5][6][7][8][9][10][11][12][13][14][15]) together with an offset, scaled according to the operand size. The offset consists of bits from the instruction, optionally added to one of three modifier registers (BM[I-3]).…”

Section: Addressesmentioning

confidence: 99%

MU6-G. a new design to achieve mainframe performance from a mini-sized computer

Edwards¹,

Knowles²,

Woods³

1980

Proceedings of the 7th Annual Symposium on Computer Architecture - ISCA '80

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MU6-G is a high performance machine useful for general or scientific applications. Its order code and architecture are designed to be sympathetic to the needs of the operating system and to both the compilation and execution of programs written in high level languages and to support a word size suitable for high precision scientific computations. Advanced technology, coupled with simplicity of design, is used to achieve a high and more readily predictable performance. Innovative features include the unique organisation of the virtual memory mapping hardware and the use of a combined operand and instruction buffer-store, accessed using virtual addresses. Fault diagnosis is aided by the inclusion of a microprocessor based diagnostic controller which has read/write access to all bistable devices in the machine and has control of the system clock. The paper includes a description of the various functional units and gives estimates of expected performance.

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“…The above discussion is at the level typically provided in machine descriptions (Organick 1973, Ibbett and Capon 1978, Buckle 1978 and only scratches the surface of the whole descriptor concept.…”

Section: Problems With Existing Designsmentioning

confidence: 99%

Effective machine descriptors for Ada

Bishop

1980

SIGPLAN Not.

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SOUTH AFRICA (tel. (Ii) 39-4011 x 8656)With the impetus provided by the U.S. Department of Defense's support for Ada, serious attention must once again be given to the design of computer architecture for the efficient execution of structured high level languages. Descriptors are one of the more theoretically popular features in a structured machine, yet in practice they do not come up to expectations. This paper examines the deficiencies of current descriptor implementations, and goes on to propose a new approach to descriptors.The design takes into account the relative usage of scalar and structured data in structured programs, and pays due attention to the efficient representation of descriptors as well as to packing, the question of unfnitialised values and the contribution which the compiler makes to range and index checking.

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The development of the MU5 computer system

Cited by 28 publications

References 7 publications

Multi-level texture caching for 3D graphics hardware

Multi-level texture caching for 3D graphics hardware

MU6-G. a new design to achieve mainframe performance from a mini-sized computer

Effective machine descriptors for Ada

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