The effect of copper contamination on field overlap edges and perimeter junction leakage current

Vermeire, Bert; Lee, L.; Parks, H.G.

doi:10.1109/66.670169

Cited by 36 publications

(25 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…[105] In ref. [106] Unfortunately, the CVD growth of graphene and h-BN on metal-coated wafers is still very challenging due to metal dewetting at high (>800 °C) temperatures. [106] Unfortunately, the CVD growth of graphene and h-BN on metal-coated wafers is still very challenging due to metal dewetting at high (>800 °C) temperatures.…”

Section: Fabrication Rs Cells Based On 2d Materialsmentioning

confidence: 99%

Recommended Methods to Study Resistive Switching Devices

Lanza

Wong

Pop

et al. 2018

Adv Elect Materials

521

434

View full text Add to dashboard Cite

Resistive switching (RS) is an interesting property shown by some materials systems that, especially during the last decade, has gained a lot of interest for the fabrication of electronic devices, with electronic nonvolatile memories being those that have received the most attention. The presence and quality of the RS phenomenon in a materials system can be studied using different prototype cells, performing different experiments, displaying different figures of merit, and developing different computational analyses. Therefore, the real usefulness and impact of the findings presented in each study for the RS technology will be also different. This manuscript describes the most recommendable methodologies for the fabrication, characterization, and simulation of RS devices, as well as the proper methods to display the data obtained. The idea is to help the scientific community to evaluate the real usefulness and impact of an RS study for the development of RS technology.

show abstract

Section: Fabrication Rs Cells Based On 2d Materialsmentioning

confidence: 99%

Recommended Methods to Study Resistive Switching Devices

Lanza

Wong

Pop

et al. 2018

Adv Elect Materials

521

434

View full text Add to dashboard Cite

show abstract

“…The wafers with iron doses of 4 10 cm had larger leakage current densities ranging from 17-30 nA-cm . For an iron dose of 4 10 cm , the leakage-current density ranged from 31-60 nA-cm , In work done by Vermeire et al, significant increases in leakage current densities for contaminate doses 1 10 cm were also seen in their copper surface-contamination study [17]. The leakage current densities of the uncontaminated control diodes annealed in the metal-free furnace were 6 nA-cm .…”

Section: Resultsmentioning

confidence: 86%

An investigation of the effects of iron in p/sup +/n silicon diodes for simulated plasma source ion implantation studies

Brown

Shohet²,

Booske³

et al. 1999

IEEE Trans. Semicond. Manufact.

View full text Add to dashboard Cite

Abstract-This work examines the effect of iron as a contaminate implant impurity on the characteristics of boron p + n silicon diodes. Plasma-based doping processes [e.g., plasma source ion implantation (PSII)] are subject to concerns about the introduction of contaminant impurities. Here, a relevant database on iron contaminant effects was acquired through a controlled study using conventional ion-beam implantation. Uncontaminated control diodes had leakage current densities of 6-9 nA-cm 02 at 05 volts and ideality factors <1.05. Iron contaminated diodes had increasing leakage current densities of 8-60 nA-cm 02 with increasing iron implant doses of 4 2 10 7 to 4 2 10 14 cm 02 and ideality factors <1.07 over six decades of current, regardless of dose.

show abstract

“…Hiramoto et al [65] reported that breakdown failure of 25 nm thick oxides was drastically increased by contamination of more that 5 Â 10 12 Cu/cm 2 , while Ogushi et al [66] found no effect of copper on gate oxide integrity for the same oxide thickness up to copper concentration of 5 Â 10 14 cm ± ±2 . Vermeire et al [67] reported that the onset of the effect of copper contamination in the integrity of 18 nm gate oxides grown on n/n silicon epi-wafers was observed at copper surface concentrations as low as 10 11 to 10 12 cm ± ±2 . Burte and Aderhold [68] found that copper affected dielectric breakdown strength of 20 nm oxides on p-Si if the surface contamination level was raised in excess of 10 9 to 10 10 cm ± ±2 .…”

Section: Impact Of Copper On Devices From the Point Of View Of Its Phmentioning

confidence: 99%

Impact of the Unique Physical Properties of Copper in Silicon on Characterization of Copper Diffusion Barriers

Istratov

Flink

Weber

2000

phys. stat. sol. (b)

View full text Add to dashboard Cite

The effect of copper contamination on field overlap edges and perimeter junction leakage current

Cited by 36 publications

References 13 publications

Recommended Methods to Study Resistive Switching Devices

Recommended Methods to Study Resistive Switching Devices

An investigation of the effects of iron in p/sup +/n silicon diodes for simulated plasma source ion implantation studies

Impact of the Unique Physical Properties of Copper in Silicon on Characterization of Copper Diffusion Barriers

Contact Info

Product

Resources

About