The effect of drain offset on current-voltage characteristics in sub micron polysilicon thin-film transistors

Olasupo, K.R.; Yarbrough, W.; Hatalis, Miltiadis K.

doi:10.1109/16.506785

Cited by 14 publications

(5 citation statements)

References 3 publications

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“…From figure 11(b), it can be seen that S increases with increasing L offset , which can be attributed to the decrease in gate control over the drainoffset region. This result is similar to previously reported results on amorphous silicon TFTs and polysilicon TFTs [31,39,[44][45][46][47]. Figures 11(c) and (d) show plots of C min and C max /C min , respectively, as functions of L offset .…”

Section: Effect Of Drain-offset Length On Tft and Varactor Characterisupporting

confidence: 90%

Enhanced capacitance ratio and low minimum capacitance of varactor devices based on depletion-mode Ga-doped ZnO TFTs with a drain-offset structure

Remashan

Choi

Park

et al. 2012

J. Phys. D: Appl. Phys.

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Depletion-mode Ga-doped ZnO thin-film transistors (TFTs) with a drain-offset configuration were fabricated employing a plasma-enhanced chemical vapour deposited Si 3 N 4 gate insulator and a metal organic chemical vapour deposition grown Ga-doped ZnO channel layer. For comparison, conventional TFTs with drain-to-gate overlap were also fabricated. Capacitance-voltage characteristics of gate-to-drain capacitors and current-voltage characteristics of TFTs were measured. Although drain-offset TFTs exhibit poor device characteristics compared with conventional TFTs, these TFTs show better C max /C min ratio and C min values. The C max /C min ratio is as large as 71.83 and C min is as small as 0.3 fF µm −1 normalized for channel width, demonstrating the potential of these devices as varactors for circuit applications. Their better varactor performance is ascribed to the presence of a very small capacitance in the drain-offset region. The effect of drain-offset length variation on TFT and gate-to-drain capacitor performance is also reported.

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Section: Effect Of Drain-offset Length On Tft and Varactor Characterisupporting

confidence: 90%

Enhanced capacitance ratio and low minimum capacitance of varactor devices based on depletion-mode Ga-doped ZnO TFTs with a drain-offset structure

Remashan

Choi

Park

et al. 2012

J. Phys. D: Appl. Phys.

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show abstract

“…In order to reduce the parasitic series resistance of the offset gated TFT, an additional step of spacer formation followed by implantation is employed. Although a poly-Si TFT with LDD has better turn-on characteristics than an offset-gated TFT, device degradation due to implant damage and difficulty Manuscript in doping control at the grain boundaries are important issues [8]. A poly-Si TFT with field-induced drain (FID) shows a low OFF-state leakage current, while maintaining good turn-on characteristics.…”

Section: Introductionmentioning

confidence: 99%

A novel self-aligned poly-Si TFT with field-induced drain formed by the damascene Process

Park

Kim

2005

IEEE Electron Device Lett.

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We have proposed and fabricated a self-aligned polysilicon thin-film transistor (poly-Si TFT) with a thick dielectric layer at the gate edges near the source and drain. A T-shaped polysilicon gate was successfully formed by the damascene process used in VLSI interconnection technology. During the ON state, an inversion layer is induced by the subgate as a drain so that the ON current is still high and the poly-Si region under the subgate behaves as an offset, reducing the OFF-state leakage current during the OFF-state. As the subgate dielectric becomes 3.5 times thicker than the main gate oxide, the minimum OFF-state leakage current of the new TFT is decreased from 1 4 10 10 to 1 3 10 11 without sacrifice of the ON current. In addition, the ON-OFF current ratio is significantly improved.Index Terms-Chemical-mechanical polishing (CMP), damascene, field-induced drain (FID), thin-film transistor (TFT).

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“…For these applications, Poly-Si TFTs must possess the qualities of high performance, high reliability and small size. Conventional offset-gated or lightlydoped-drain (LDD) structures have been widely used to increase the reliability and reduce the leakage current by suppressing the electric field at the drain junction [3][4][5][6]. However, some of these structures require an additional photolithographic step to define the non self-aligned offset region [3], and other self-aligned LDD structures require a complicated process, and the LDD length is limited to a small value due to the process limitations [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

P‐6: A Novel Self‐Aligned Lightly‐Doped‐Drain Polysilicon Thin‐Film Transistor Using a Partial Exposure Technique

Xiong

Liu

Sin

2004

Symp Digest of Tech Papers

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In this paper, a novel self‐aligned lightly‐doped‐drain (LDD) Poly‐Si TFT using a partial exposure technique is proposed and demonstrated. The LDD region is self‐aligned to the channel and with a length ranging from 0.4 μm to a few μm. The different LDD lengths can be obtained simply by different layout designs. The partial exposure technique for obtaining the LDD is simple and effective, and does not require any additional mask. Experimental results show that the on/off current ratio of the LDD Poly‐Si TFT with 0.5 μm LDD length and 5 μm channel length is approximately 12 times larger than that of the conventional non‐LDD TFT.

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The effect of drain offset on current-voltage characteristics in sub micron polysilicon thin-film transistors

Cited by 14 publications

References 3 publications

Enhanced capacitance ratio and low minimum capacitance of varactor devices based on depletion-mode Ga-doped ZnO TFTs with a drain-offset structure

Enhanced capacitance ratio and low minimum capacitance of varactor devices based on depletion-mode Ga-doped ZnO TFTs with a drain-offset structure

A novel self-aligned poly-Si TFT with field-induced drain formed by the damascene Process

P‐6: A Novel Self‐Aligned Lightly‐Doped‐Drain Polysilicon Thin‐Film Transistor Using a Partial Exposure Technique

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