A novel self-aligned poly-Si TFT with field-induced drain formed by the damascene Process

Abstract

We have proposed and fabricated a self-aligned polysilicon thin-film transistor (poly-Si TFT) with a thick dielectric layer at the gate edges near the source and drain. A T-shaped polysilicon gate was successfully formed by the damascene process used in VLSI interconnection technology. During the ON state, an inversion layer is induced by the subgate as a drain so that the ON current is still high and the poly-Si region under the subgate behaves as an offset, reducing the OFF-state leakage current during the OFF-state. As the subgate dielectric becomes 3.5 times thicker than the main gate oxide, the minimum OFF-state leakage current of the new TFT is decreased from 1 4 10 10 to 1 3 10 11 without sacrifice of the ON current. In addition, the ON-OFF current ratio is significantly improved.Index Terms-Chemical-mechanical polishing (CMP), damascene, field-induced drain (FID), thin-film transistor (TFT).

Drain bias and position dependent performance degradation of dual-gate poly-Si TFTs with undoped region offsets

“…Compared with conventional amorphous Si TFTs and amorphous oxide semiconductor TFTs, polycrystalline silicon (poly-Si) TFTs have higher mobilities, driving capability, and reliability. They are also highly compatible with conventional complementary metal-oxide-semiconductor processes [1][2][3][4][5].…”

A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

“…The main approach to lower the leakage current and suppress the kink effect is to reduce the device drain side electric field. Several designs have been proposed and studied to reduce the drain electric field and improve device performance, including offset gate [6,7], lightly-doped drain (LDD) [8,9], and field-induced drain (FID) [10,11] TFTs. However, offset gate TFT sacrifices the On-state current, due to an increased parasitic resistance, and FID design often needs an extra mask and one more field bias, which complicates the device biasing scheme.…”

Superior Reliability of Gate-All-Around Polycrystalline Silicon Thin-Film Transistors with Vacuum Cavities Next to Gate Oxide Edges

“…12) It is well known that the leakage current mechanism in the OFF state is field emission via grain boundary trap states due to a high electric field in the depletion region of a drain. 13) Therefore, planar T-gate poly-Si TFTs, formed by the damascene process 14) or the selective wet etching of stacked Si/Ge 15) or Mo/Al 16) gate electrodes, have been proposed to reduce the OFF-state leakage current and to increase the stability, resulting from decreasing the lateral and vertical electric fields simultaneously via the increased effective thickness of the dielectric layer underneath the gate electrode edges. In this study, we propose GAA poly-Si TFTs with vacuum cavities next to the gate oxide edges, which are successfully fabricated by spacer formation, partial wet etching of a gate oxide, and in situ vacuum encapsulation, to improve not only the electrical characteristics but also the reliability of devices under static and dynamic electrical stresses.…”