The effect of indirect UV/ozone treatment on pentacene thin film transistors with double-stacked organic gate insulators

Kim, Min Su; Lee, Dong‐Hoon; Cho, Hyeong Jun; Oh, Jongsu; Lee, So Young; Kim, Jae-Moon; Park, KeeChan; Kim, Yong−Sang

doi:10.1016/j.orgel.2017.10.036

Cited by 7 publications

(5 citation statements)

References 19 publications

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“…25,26 Previous studies have reported that the smooth surface resulting of the optimized DLGD condition improves device performance including operational stability. 13,14 The parylene-based gate dielectrics show a root-mean-square (R q ) of surface roughness of less than 3 nm regardless of the X (Figure 3a−d and Figure S2). Moreover, the DI water CAs were estimated to be approximately 90°regardless of gate dielectric conditions (Figures 3e−h and Figure S3).…”

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confidence: 99%

“…DLGDs have been utilized to adjust the surface energy, reduce the gate-source current ( I GS ), tune the threshold voltage ( V TH ), and provide a smooth surface . Moreover, they have been used to compensate for two different SLGD-induced operational instability mechanisms by varying the thickness ratio of each gate dielectric. − As a result, the operational stability of OFETs has been considerably improved, but the structural effects of DLGDs on the device performance has not been discussed in detail yet. − …”

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confidence: 99%

“…Furthermore, surface roughness and deionized (DI) water contact angle (CA) of parylene-based gate dielectrics were measured to investigate the interface properties (Figure ). It is noted that the surface roughness of the gate dielectric is one of the most important factors in charge carrier transport at the interface, but it has not been carefully addressed during OFET fabrication and electrical measurement. , Previous studies have reported that the smooth surface resulting of the optimized DLGD condition improves device performance including operational stability. , The parylene-based gate dielectrics show a root-mean-square ( R q ) of surface roughness of less than 3 nm regardless of the X (Figure a–d and Figure S2). Moreover, the DI water CAs were estimated to be approximately 90° regardless of gate dielectric conditions (Figures e–h and Figure S3).…”

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confidence: 99%

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Parylene-Based Double-Layer Gate Dielectrics for Organic Field-Effect Transistors

Park

Ahn

Kwon

et al. 2018

ACS Appl. Mater. Interfaces

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We demonstrate high-performance and stable organic field-effect transistors (OFETs) using parylene-based double-layer gate dielectrics (DLGDs). DLGDs, consisting of parylene C as the upper layer and F as the lower layer, are designed to simultaneously provide good interface and bulk gate dielectric properties by exploiting the advantages of each gate dielectric. The structural effects of DLGDs are systematically investigated by evaluating the electrical characteristics and dielectric properties while varying the thickness ratio of each gate dielectric. The OFET with the optimized DLGD exhibits high performance and operational stability. This systematic approach will be useful for realizing practical electronic applications.

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Parylene-Based Double-Layer Gate Dielectrics for Organic Field-Effect Transistors

Park

Ahn

Kwon

et al. 2018

ACS Appl. Mater. Interfaces

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“…This means that the surface is changed to hydrophilic by increasing oxygen bonding to the surface through O 2 plasma treatment. In addition, the root-mean-square (RMS) surface roughness of the patterned PMMA layer was also confirmed because pentacene, the active layer material, has a larger grain size at the smooth surface [24,25]. The surface roughness of CYTOP increased to RMS=1.364 nm after O 2 plasma treatment, but after coating with PMMA, it exhibited a smooth surface with RMS=0.526 nm on which the organic material can be deposited.…”

Section: Pmma Patterning On Cytop Layermentioning

confidence: 86%

Ultrathin flexible thin film transistors with CYTOP encapsulation by debonding process

Kim

Jung

et al. 2019

Semicond. Sci. Technol.

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We fabricated ultrathin flexible thin film transistors with hydrophobic encapsulation layer by debonding process. In the debonding process, to separate the transistors from the carrier glass in deionized (DI) water, a strong hydrophobic material such as CYTOP was used for encapsulation, thus increasing their resistance to moisture. PVA was used as a release layer and the debonding process was optimized to separate the carrier glass and the transistors. It was confirmed that water penetration into the device can be suppressed effectively when the CYTOP thickness is 800 nm. In addition, the electrical characteristics remained almost constant even in the presence of water for 50 min. The total thickness after debonding process was approximately 2 μm. Waterproof experiments and debonding process were performed for a simple inverter circuit as well as a discrete device, and the operation and voltage gain of the inverter did not change when water was placed on the device or after debonding process. Finally, the flexibility was measured by transferring the device to a flexible PI substrate. Consequently, it was confirmed that degradation in the electrical properties was slightly up to a bending radius of 2.5 mm.

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“…The manufacturing processes also impact stability, both storage and operational, another matter in this field with severe consequences to the final OTFT application. In this sense, several efforts have been made to address the performance/stability issues in OTFTs from the perspective of manufacturing . Despite the advances in this direction, a significant gap still exists between the current OTFT technology and the well-established inorganic semiconductors when it comes to rugged electronics.…”

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confidence: 99%

Low-Voltage, Flexible, and Self-Encapsulated Ultracompact Organic Thin-Film Transistors Based on Nanomembranes

et al. 2018

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Organic thin-film transistors (OTFTs) are an ever-growing subject of research, powering recent technologies such as flexible and wearable electronics. Currently, many studies are being carried out to push forward the state-of-the-art OTFT technology to achieve characteristics that include high carrier mobility, low power consumption, flexibility, and the ability to operate under harsh conditions. Here, we tackle this task by proposing a novel OTFT architecture exploring the so-called rolled-up nanomembrane technology to fabricate low-voltage (<2 V), ultracompact OTFTs. As the OTFT gate electrode, we use strained nanomembranes, which allows all transistor components to be rolled-up and confined into a tubular-shaped tridimensional device structure with reduced footprint (ca. 90% of their planar counterpart), without any loss of electrical performance. Such an innovative architecture endows the OTFTs high mechanical flexibility (bending radius of <30 μm) and robustness-the devices can be reversibly deformed, withstanding more than 500 radial compression/decompression cycles. Additionally, the tubular device design possesses an inherent self-encapsulation characteristic that protects the OTFT active region from degradation by UV-light and hazardous vapors. The reported strategy is also shown to be compatible with different organic semiconductor materials. All of these characteristics contribute to further extending the potentialities of OTFTs, mainly toward rugged electronics.

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The effect of indirect UV/ozone treatment on pentacene thin film transistors with double-stacked organic gate insulators

Cited by 7 publications

References 19 publications

Parylene-Based Double-Layer Gate Dielectrics for Organic Field-Effect Transistors

Parylene-Based Double-Layer Gate Dielectrics for Organic Field-Effect Transistors

Ultrathin flexible thin film transistors with CYTOP encapsulation by debonding process

Low-Voltage, Flexible, and Self-Encapsulated Ultracompact Organic Thin-Film Transistors Based on Nanomembranes

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