The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in p/sup +/-gate p-channel MOSFETs with fluorine incorporation

Tseng, Hsing‐Huang; Tobin, Philip J.; Baker, F.K.; Pfiester, J.R.; Evans, Katharine; Fejes, P.

doi:10.1109/16.141235

Cited by 35 publications

(5 citation statements)

References 8 publications

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“…The breakdown fields of the failed samples were typically distributed in the range of B-mode failure, 5 as shown in Fig. 4, implying that the failures were related to defects such as gate oxide thinning, [6][7][8] crystal defects in the silicon substrate, [8][9] or metallic impurities. 10 The transmission electron microscopy (TEM) images shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

Control of the Slope of Field Oxide Edge and Its Effects on Gate Oxide Reliability

Jang

Kim

Yeo

et al. 1999

J. Electrochem. Soc.

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Effect of field oxidation ambients on the gate oxide reliability in recessed local oxidation of silicon (LOCOS) with a nitride spacer has been studied. Conventional wet ambient field oxidations produced negative field oxide edge slopes and resulted in gate oxide thinning at the field oxide edges, leading to degraded gate oxide characteristics. We have found that the slope of field oxide edge can be modified from negative to positive by oxidizing in a dry ambient or in a wet and subsequent dry ambient. No gate oxide thinning was observed when the edge slope was controlled to be positive. Considering field-oxide-ungrowth phenomenon, field oxide thinning effect, gate oxide thinning, and gate oxide reliability, a three-step field oxidation method was proposed for the recessed LOCOS.

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Section: Resultsmentioning

confidence: 99%

Control of the Slope of Field Oxide Edge and Its Effects on Gate Oxide Reliability

Jang

Kim

Yeo

et al. 1999

J. Electrochem. Soc.

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“…A split between a 550 C deposition process (amorphous silicon) and a 625 C deposition process (polysilicon) was performed. Results in the literature show that amorphous silicon reduces the effect of boron penetration through the gate oxide, by reducing the diffusion coefficient of boron in the gate [1], [4], [7]. Fig.…”

Section: Physical Characterizationmentioning

confidence: 99%

Improvement in threshold voltage control by minimizing boron penetration in a LV-GCMOS technology

John

Teplik²,

Hildreth³

et al. 1998

IEEE Trans. Semicond. Manufact.

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Maintaining tight threshold voltage (V T V T V T ) control for a low-voltage CMOS process is critical due to the large impact of V T V T V T on circuit performance at low power supply voltages. In this paper, PMOS V T V T V T was shown to be sensitive to poly gate thickness and BF + + + 2 source/drain implant energy. This data helped identify boron penetration as a prime contributor to PMOS threshold voltage variation. SIMS measurements were used to investigate boron diffusion through the poly gate at various stages in the process flow. These SIMS profiles pointed to the low-temperature thermal cycle of the nitride spacer deposition as a key step which influenced the amount of boron penetration and thus the final device threshold voltage. Experimental evidence shows that the temperature gradient across the nitride spacer deposition furnace causes a variable amount of boron penetration resulting in a large variation in PMOS VT VT VT . We adopted a process flow change which virtually eliminated boron penetration and significantly reduced the sensitivity of the devices to manufacturing variations. Threshold voltage variation was reduced by a factor of two.

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“…Although to reoxidize the nitrided oxide at high temperature can improve dielectric properties by reducing the density of electron traps, such a high temperature step may not be desirable for future deep-submicrometer CMOS process. Instead of such a nitrided oxide, another approach is to modify the structure of the poly-gate, such as larger grain size formed by as-deposited amorphous silicon [16], [18], and stacked amorphous silicon film [I71 to suppress the boron penetration. Less boron penetration is due to suppression of fluorine and boron diffusion in as-deposited amorphous silicon gate and a longer diffusion path in the stacked amorphous silicon layers.…”

Section: P+mentioning

confidence: 99%

“…Detail description of the segregation and diffusion mechanism for fluorine and boron atoms will be discussed in the later report [28]. The effects of lower fluorine diffusion rate in the underlaid amorphous silicon [16], [29] and segregation of fluorine impurities at the poly/amorphous interface result in a much larger amount of fluorine in the gate electrode. The more fluorine is retained in the polygate electrode, the less fluorine diffuses into the gate oxide.…”

Section: B P+ -Poly Gated Mos Transistorsmentioning

confidence: 99%

Suppression of boron penetration in BF/sub 2/-implanted p-type gate MOSFET by trapping of fluorines in amorphous gate

Lin

Chang

Hsu³

1995

IEEE Trans. Electron Devices

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The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in p/sup +/-gate p-channel MOSFETs with fluorine incorporation

Cited by 35 publications

References 8 publications

Control of the Slope of Field Oxide Edge and Its Effects on Gate Oxide Reliability

Control of the Slope of Field Oxide Edge and Its Effects on Gate Oxide Reliability

Improvement in threshold voltage control by minimizing boron penetration in a LV-GCMOS technology

Suppression of boron penetration in BF/sub 2/-implanted p-type gate MOSFET by trapping of fluorines in amorphous gate

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