The effectiveness of TRONCHIP instructions in the TX1 system

T h e T X 2 processor zs the second zmplementatzon an the Toshzba TLCSSOOOO/TX semes of 32-bzt mzcroprocessors based on the TRON[l] speczjicatzon. T h e TX2 mzcro-archztecture defines jive functzonal m a t s whach zmplement a four-stage pzpehne. Baszc znstructaons wzth regzster-regaster operatzon are executed an a szngle cycle wath a sangde step of macrocode. T h e TX2 h a s a performance of 25 MIPS and executes about 20,000 dhystones/second at 25MHz wath zero waat external bus cycle. Deszgn of the T X 2 as based o n full custom LSI deszgn methodology. To zncrease the operatzng frequency of the CISC macroprocessor TX2, tzmzng design based on statzc path delay analysts was performed. A s a result , hzgh speed processor has been achzeved.

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“…The two TX[2] series MPUs developed are the TX1 [3] [4] and TX2. The TX2 is the higher entry in the product line.…”

Section: Introductionmentioning

confidence: 99%

Design of 32-bit TX2 microprocessor based on TRON specifications

Goto

Otaguro²,

Utsumi³

et al.

Proceedings the Tenth Project International Symposium, 1993

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“…The TX2[1] is a 32-bit microprocessor based on the TRON architecture[2], having been developed as a successor of TX1 [3] [4]. Figure 1 shows a chipphotograph of the TX2.…”

Section: Introductionmentioning

confidence: 99%

A 32-bit microprocessor with efficient testable designs, the TX2

Nozuyama¹,

Mitani²,

Fukumoto³

et al.

Proceedings of the 11th TRON Project International Symposium

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A 32-bit microprocessor, the T X 2 , with efficien.2 testable designs, has been developed. For manufacturing test, a combinaiion of powerful BISTs and parallel scan design is implemented. The BISTs achieze 100% funciional coverage for ROM, RAM and P L A and 78%: coverage of single stuck-at faults of the remaining pari of ihe T X 2 including redundant faults. Scan test vectors obtained b y A T P G have enhanced the corerage i o 84%. Total lest time is less ihan 2 seconds. There are also a few circuitry for efficient design zerification. Moreover, f o r higher test quality, Idd,q test is implemented. Total area overhead is 6.9%

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Bibliography of the TRON project (1984-91)

Bowles¹,

Takada²

1991

Proceedings Eighth TRON Project Symposium

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The effectiveness of TRONCHIP instructions in the TX1 system

Cited by 4 publications

References 7 publications

Design of 32-bit TX2 microprocessor based on TRON specifications

Design of 32-bit TX2 microprocessor based on TRON specifications

A 32-bit microprocessor with efficient testable designs, the TX2

Bibliography of the TRON project (1984-91)

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