The effects of plasma-induced damage on transistor degradation and the relationship to field programmable gate array performance

Pagaduan, F. E.; Lee, J.K.J.; Vedagarbha, V.; Lui, K.; Hart, Michael J.; Gitlin, Daniel; Takaso, T.; Kamiyama, Satoshi; Nakayama, Keiichi I.

doi:10.1109/relphy.2001.922921

Cited by 8 publications

(6 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Pagaduan et al from Xilinx also show that plasma damage degrades NBTI in p-MOSFETs, but n-MOSFETs are not degraded. 98 The threshold voltage degradation is consistent with their observation that the rise time of the CMOS output signal, controlled by the p-MOSFET, is degraded. The fall time, controlled by the n-MOSFET, is unchanged.…”

Section: Nbti Minimizationsupporting

confidence: 83%

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

Schroder

Babcock

2003

Journal of Applied Physics

940

396

View full text Add to dashboard Cite

Articles you may be interested inInterface traps responsible for negative bias temperature instability in a nitrided submicron metal-oxidesemiconductor field effect transistor Appl. Phys. Lett. 98, 103513 (2011); 10.1063/1.3559223 Bias temperature instability in metal-oxide-semiconductor field-effect transistors with atomic-layer-deposited Sinitride/ Si O 2 stack gate dielectrics J. Appl. Phys. 103, 084512 (2008); 10.1063/1.2907768Using the Hall effect to measure interface trap densities in silicon carbide and silicon metal-oxide-semiconductor devices Appl.A study on the capacitance-voltage characteristics of metal-Ta 2 O 5 -silicon capacitors for very large scale integration metal-oxide-semiconductor gate oxide applications Identification of isolation-edge related random telegraph signals in submicron silicon metal-oxide-semiconductor field-effect transistors

show abstract

Section: Nbti Minimizationsupporting

confidence: 83%

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

Schroder

Babcock

2003

Journal of Applied Physics

940

396

View full text Add to dashboard Cite

show abstract

“…Water may also drift from the intermetal dioxide or PSG (phosopho-silicate glass) layers to effect NBTI [10]. The hydrogen commonly used in post metal anneals may also act as a catalyst for NBTI [11].…”

Section: Negative Bias Temperature Instability (Nbti)mentioning

confidence: 99%

“…The temperature and bias stress times vary widely, from a few minutes to hundreds of hours ( [1] pp. 365, [7,8,9,11,12,13,14]).…”

Section: Negative Bias Temperature Instability (Nbti)mentioning

confidence: 99%

See 1 more Smart Citation

The Role of Temperature in Testing Deep Submicron CMOS ASICs

Long¹

2000

View full text Add to dashboard Cite

Title: The Role Of Temperature In Testing Deep Submicron CMOS ASICs.Among the many efforts to improve the IC test process are tests that attempt to differentiate between healthy and defective or low reliability ICs by manipulating the operating conditions of the IC being tested. This thesis attempts to improve the common understanding of multiple and targeted temperature testing by evaluating work published on the subject to date and by presenting previously unpublished empirical observations. The empirical observations are made from SCAN and LBIST based MinVDD measurements, Static IDD measurements, as well as parametric measurements of transistor characteristics. The test vehicles used are 0.25µm and 0.18µm CMOS ASICs fabricated by LSI Logic. An IC's performance is bound by a three dimensional space defined by VDD, frequency, and temperature. A model is presented to explain the boundaries of the performance region in terms of the ability of the IC's constituent transistors to provide power and the Zero-Temperature-Coefficient (ZTC). Also, it is determined that multiple temperature testing can add new tests to current test suites to improve the resolution between healthy and defective ICs.c

show abstract

“…En los dispositivos MOS también se observa una degradación de las características I DS -V GS [Rangan et al 1999, Pagaduan et al 2001, manifestándose generalmente como un incremento de la tensión umbral (V T ) [Lin et al 1996].…”

Section: Efectosunclassified

Contribución a la validación de sistemas complejos tolerantes a fallos en la fase de diseño. Nuevos modelos de fallos y técnicas de inyección de fallos.

Calvo¹,

Carlos²

View full text Add to dashboard Cite

The effects of plasma-induced damage on transistor degradation and the relationship to field programmable gate array performance

Cited by 8 publications

References 8 publications

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

The Role of Temperature in Testing Deep Submicron CMOS ASICs

Contribución a la validación de sistemas complejos tolerantes a fallos en la fase de diseño. Nuevos modelos de fallos y técnicas de inyección de fallos.

Contact Info

Product

Resources

About