The eISP low-power and tiny silicon footprint programmable video architecture

Abstract

International audienceCMOS sensors are now more and more frequently integrated into popular consumer products. Images from these sensors thus need to be digitally processed for display purposes. To do so, CMOS sensors are associated with dedicated components that keep power consumption low. However, use of dedicated components limits hardware flexibility and prevents updating of image processing algorithms. This paper describes the eISP, a programmable processing architecture that combines enough computational efficiency for 1080p HD video with silicon area and power characteristics suitable for the next generation of mobile phones (lower than 1 mm2 and 500 mW in TSMC 65 nm)

A Future for Integrated Diagnostic Helping

“…The proposed architecture is based on the eISP (Thevenin, 2010) processor that is designed for smart phone embedded video and is derived to give enough computing capacity to support diagnostic helping image processing algorithms that could be required in an endocapsule. Our study established an approximation of the required computing capacity of about 50 GOPs for an average power consumption of less than a half Watt, and a maximum silicon area of 15 mm² dedicated to computations.…”

Designing processors using MAsS, a modular and lightweight instruction-level exploration tool

“…The MAsS tool has been used to design the embedded Image Signal Processor (eISP) architecture [16], [17] able to support different categories of low-level image processing. The targeted architecture has to process pixel streams from a video sensor.…”

“…Each computing tile contains an IO interface that enables integration of pixel values from incoming streams and reconstructs outgoing stream. MAsS helped in designing eISP, a fully programmable state of the art [17] architecture for real-time video processing.…”