The EPAC architecture: an expert cell approach to field programmable analog circuits

Abstract

This paper describes the architectural variety of higher-level functions with configuration and various design trade-offs of programmable perfomance characteristics. the Electrically Programmable Analog Circuit This corresponds to a "macro" approach m (EPACThf), an expert-cell approach to meeting digital FPGAs which is now becoming more the m e e t need for an analog counterpart to popular as higher-level functions, such as fast the digital P G A . It provides an overview of multipliers and memory modules, need to be the technology, discussed architectural issues, integral parts of an FPGA architecture. and describes the intemal operation of the first "&pert cells," m our context, are modules commercial EPAC devices. The paper which implement a certain number of concludes with various application examples. Overview EPAC devices are the hrst commercial analog ICs that can be programmed m functionality, interconnect, and performance characteristics. The EPAC device architecture is based on a CMOS process with onchip SRAM and EEPROM memory to provide one-time and in-system user programmability. Programming can be performed either off-line programmable functions in a controlled environment, limited to the boundaries of the cell. As a result, the cell can be designed to work under all programmable circumstances permitted within the cell boundary even considering the significant number of parasitic effects that must be dealt with m programmable analog circuits. The EPAC Device Framework EPAC devices are built on a framework or in real-time. which incorporates the functional modulesAs opposed to providing access to all together with programming features, low-level components to form certain debugging aids and interconnect "highways."functions, an "expert cell" approach has beenThe key elements of that framework include a chosen wherein the building blocks feature a serial interface, an EEPROM-memory

Developing large-scale field-programmable analog arrays for rapid prototyping

“…Thus, a large number of switches are introduced into the signal path. The switch parasitics and finite resistance increases the noise within the system and limits the performance/bandwidth (Pierzchala et al, 1995;Embabi et al, 1996;Klein, 1996). Fine grain FPAAs have primarily been relegated to research in evolvable hardware (Keymeulen et al, 2000;Santini et al, 2001;Stoica et al, 2001), where the lowest level building blocks are desirable for generating unique designs using nontraditional design methodologies.…”

“…Systems that are designed using genetic algorithms are not as negatively affected by the parasitics and nonideal resistances of switches, since these parameters are taken into account and even exploited throughout the evolutionary design process. On the coarse grain extreme, one finds FPAAs such as IMP's EPAC™devices, which contain an 'expert cell' as the core computational block (Klein, 1996). For the IMP50E10 device, this cell is a very high level block with limited interconnects that is aimed directly at signal conditioning applications.…”

“…There is also a dedicated D/A converter for defining the reference point for the comparator. These coarse grain designs sacrifice flexibility and generality in favour of increased, more predictable performance (Klein, 1996). The majority of FPAAs fall in between these two extremes.…”

“…Many FPAA designs have sacrificed size and generality in favour of better performance for a constrained set of circuit designs. FPAAs have been proposed for evolvable hardware (Keymeulen et al, 2000;Santini et al, 2001;Stoica et al, 2001), neural networks (Lee andGulak, 1991a, 1991b), signal conditioning (Klein, 1996), programmable filters (Embabi et al, 1996;Quan et al, 1998), fuzzy logic (Pierzchala et al, 1994), and high frequency applications (Gaudet and Gulak, 1997). Others FPAA designs have attempted to focus on a broader class of systems including both linear and nonlinear elements (Bratt, 1998;Ray et al, 2000).…”

Field-Programmable Analog Arrays: A Floating—Gate Approach

“…Thus, a large number of switches are introduced into the signal path. The switch parasitics and finite resistance increases the noise within the system and limits the performance/bandwidth [24,49,67]. Fine-grain FPAAs have been primarily relegated to research in evolvable hardware [48,72,78], where the lowest-level building blocks are desirable for generating unique designs using non-traditional design methodologies.…”