This paper describes the architectural variety of higher-level functions with configuration and various design trade-offs of programmable perfomance characteristics. the Electrically Programmable Analog Circuit This corresponds to a "macro" approach m (EPACThf), an expert-cell approach to meeting digital FPGAs which is now becoming more the m e e t need for an analog counterpart to popular as higher-level functions, such as fast the digital P G A . It provides an overview of multipliers and memory modules, need to be the technology, discussed architectural issues, integral parts of an FPGA architecture. and describes the intemal operation of the first "&pert cells," m our context, are modules commercial EPAC devices. The paper which implement a certain number of concludes with various application examples. Overview EPAC devices are the hrst commercial analog ICs that can be programmed m functionality, interconnect, and performance characteristics. The EPAC device architecture is based on a CMOS process with onchip SRAM and EEPROM memory to provide one-time and in-system user programmability. Programming can be performed either off-line programmable functions in a controlled environment, limited to the boundaries of the cell. As a result, the cell can be designed to work under all programmable circumstances permitted within the cell boundary even considering the significant number of parasitic effects that must be dealt with m programmable analog circuits. The EPAC Device Framework EPAC devices are built on a framework or in real-time. which incorporates the functional modulesAs opposed to providing access to all together with programming features, low-level components to form certain debugging aids and interconnect "highways."functions, an "expert cell" approach has beenThe key elements of that framework include a chosen wherein the building blocks feature a serial interface, an EEPROM-memory

This paper describes the architectural configuration of the Electrically Programmable Analog Circuit (EPAC™), an expert cell approach to meeting the market need for an analog counterpart to the digital FPGA. It provides an overview of the technology and describes the internal operation of the first commercial EPAC devices. OverviewEPAC devices are analog ICs that can be programmed in functionality, interconnect, and performance characteristics. The EPAC device architecture is based on a mixed-signal CMOS process with on-chip SRAM and EEPROM memory to provide user programmability. Programming can be performed either off-line or in real-time. The SRAM components enable in-system functional reconfiguration, while leaving the original EEPROM configuration unchanged.EPAC technology raises the design task of system analog functions from a tedious and error-prone component level to a functional, or block, level. This is made possible by programmable analog "expert cell" modules each of which feature a variety of functions and performance characteristics. Using a PC-based development system, the user creates a circuit by selecting the functionality of the modules along with their respective performance settings and cell-to-cell interconnections.This approach greatly simplifies and shortens the design for analog circuits.Programmable analog devices offer significant benefits over traditional analog design approaches because they address key needs of today's system developers, by providing• High levels of integration • Instant prototyping and reprogramming • Design on block level using intuitive design tools • In-system reconfiguration for use in microcontrollerbased systems • No NRE for design or redesign • Minimum inventory and purchase commitment • Generalized test programs. The EPAC architecture also permits straightforward migration of designs to a compatible mask-programmable solution using a simpler process and smaller die size for highvolume applications. EECMOS Process TechnologyThe first implementation of EPAC technology is based on a 1.2 micron analog EECMOS process. This required adding a self-contained EEPROM process module (including a high-voltage generator) to a proven analog CMOS process without affecting the critical analog performance characteristics. This permits the device design engineers to draw from an existing library of high-performance cells, ranging from very fast circuits to high-precision converters, references, etc. This also ensures that the performance of the modules embedded in EPAC devices are competitive with dedicated ICs, while offering higher degrees of flexibility and functionality.

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