State of the art in the analog CMOS circuit design

Habekotte, E.; Hoefflinger, B.; Klein, H.W.; Beunder, M.A.

doi:10.1109/proc.1987.13803

Cited by 15 publications

(2 citation statements)

References 43 publications

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“…Examples of bottom-up approaches are transistor arrays [13], analog library cells [10]. and fixed topology module generators [9]. All three approaches primarily help ease the path to layout, but do not necessary help a designer generate a circuit schematic from a set of performance specifications.…”

Section: Figure 1 Analog Synthesis Sequencementioning

confidence: 99%

OASYS: a framework for analog circuit synthesis

Harjani

Rutenbar

Carley

1989

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

362

120

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We describe a hierarchical structure for a knowledge-based analog circuit synthesis tool. Analog circuit topologies are represented as a hierarchy of abstract functional blocks each with associated design knowledge. We also describe mechanisms to select from among alternate design styles, and to translate performance specifications from one level in the hierarchy to the next lower level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers and comparators from a set of performance specifications and process parameters. We describe the role such a synthesis system can play in exploring the space of designable circuits. And finally, we briefly describe other related research in analog synthesis at Carnegie Mellon, including OASYS-VM, which facilitates the addition of new design topologies to the framework, and ANAGRAM, the counterpart to OASYS, which performs the circuit schematic to physical layout phase of analog circuit design Functional Specifications

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Section: Figure 1 Analog Synthesis Sequencementioning

confidence: 99%

OASYS: a framework for analog circuit synthesis

Harjani

Rutenbar

Carley

1989

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

362

120

View full text Add to dashboard Cite

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“…When this technology was first proposed there were concerns on its application for analog circuits like the low driving capabilities of MOSFET devices compared to bipolar transistors. This motivated the implementation of BiCMOS technologies which takes advantage of the best features of both transistors in the same chip [1,2]. In recent years, one problem with the MOSFET scaling is the increase of power dissipation.…”

Section: Introductionmentioning

confidence: 99%

Hybrid low-dropout voltage regulator designed with TFET-MOSFET nanowire technologies

Tolêdo

Martino

Agopian

2023

Semicond. Sci. Technol.

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In this work, hybrid low-dropout voltage regulators (LDO) designed with a TFET-MOSFET nanowire (NW) technologies are presented. The devices were modeled using Verilog-A with lookup tables based on experimental data of NW-TFETs and NW-MOSFETs fabricated in the same silicon vertical process flow. In all LDOs, the amplifier devices were biased with the same gm/ID = 9.5 V-1 for a maximum load current/capacitance of 1 mA/1 nF. In the hybrid regulators, the power transistors are designed with NW-MOSFETs to deliver the high load current, while the other devices are implemented with NW-TFET to provide high gain and low power consumption. Due to different onset voltages, two hybrid LDOs are proposed, one with symmetrical onset voltages implemented with a voltage shift (Hybrid-ΔV LDO) and one with a level-shift stage using the real characteristics of the devices (Hybrid-LS LDO). The hybrid circuits were compared to LDOs designed using only NW-TFETs and with only NW-MOSFETs. The Hybrid-ΔV LDO presents the best loop gain (62 dB) with a low quiescent current (7 nA), while the Hybrid-LS LDO shows a good gain-bandwidth product (700 Hz). In the transient analysis, the hybrid circuits showed a settling time close to the NW-MOSFETLDO but with higher undershoot/overshoot values in the case of a load transient. As demonstrated, the use of hybrid projects with TFET-MOSFET nanowire technologies enable LDOs with ultra-low power consumption and high loop gain, that are presented on TFET circuits and with a frequency response equivalent of MOSFET circuits.

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Issues in Analog VLSI and MOS Techniques for Neural Computing

Bibyk

Ismail

1989

The Kluwer International Series in Engineering and Computer Science

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State of the art in the analog CMOS circuit design

Cited by 15 publications

References 43 publications

OASYS: a framework for analog circuit synthesis

OASYS: a framework for analog circuit synthesis

Hybrid low-dropout voltage regulator designed with TFET-MOSFET nanowire technologies

Issues in Analog VLSI and MOS Techniques for Neural Computing

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