The evolution of growth stresses in chemical vapor deposited tungsten films studied by <i>in</i> <i>situ</i> wafer curvature measurements

Leusink, G. J.; Oosterlaken, T. G. M.; Janssen, G. C. A. M.; Radelaar, S.

doi:10.1063/1.354485

Cited by 27 publications

(5 citation statements)

References 36 publications

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“…20 Results suggest that the nickel alloy deposition on SiO 2 has significantly less tensile stress (∼1.14 Gpa), even after annealing at 400 °C in forming gas, than when using W (∼2 Gpa). 20,21 This addresses the problem of wafer bending induced by W metal and/or silicon channel annealing 19 and further supports the case of NiB being a potential replacement of W metal.…”

Section: Materials and Physical Resultssupporting

confidence: 54%

Gate MOSCAP Studies on Electroless Deposited Nickel Boron as Word Line Candidate Metal for Future Scaled 3-D NAND Flash

Ramesh

Rachidi

Donadio

et al. 2023

ECS J. Solid State Sci. Technol.

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3-D NAND Flash has become the workhorse for non-volatile memory based storage. It is therefore important to develop solutions that keep NAND scaling in a sustainable path with respect to cost and performance. The memory cells in 3-D NAND are addressed by horizontal word lines (WLs) that are stacked vertically. With each technology node, the WL metallization, performed using CVD / ALD tungsten metal with a thin TiN barrier, poses a challenge in terms of WL cavity filling and WL resistance. A wet nickel boron (NiB) electroless and barrierless deposition is proposed for the next generation 3-D NAND Flash technology. Here, we investigate the memory behavior using metal / high-k / ONO / Si (MHONOS) capacitors while the resistivity and tensile stress were studied on blankets. Results indicate that the program and erase performance of the NiB devices are comparable to that of the W/TiN reference. Furthermore, the tensile stress is two times lower for the NiB integration.

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Section: Materials and Physical Resultssupporting

confidence: 54%

Gate MOSCAP Studies on Electroless Deposited Nickel Boron as Word Line Candidate Metal for Future Scaled 3-D NAND Flash

Ramesh

Rachidi

Donadio

et al. 2023

ECS J. Solid State Sci. Technol.

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“…Koseski showed that intrinsic (athermal) stress in W may be responsible for higher stress values in W-TSVs [27]. For W-CVD at 400°C, diffusion, crystal regeneration, recrystallization or creep are blocked due to high melting temperature of W, thus giving a significant contribution to intrinsic stress [28].…”

Section: Discussionmentioning

confidence: 98%

Residual stress investigations at TSVs in 3D micro structures by HR-XRD, Raman spectroscopy and fibDAC

Zschenderlein

Vogel

Auerswald

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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In this paper the residual stress in single-crystalline Si around W-filled TSVs was determined experimentally by three methods with high spatial resolution and compared to one another. In contrast to Cu as TSV filler, W has the potential advantage of a lower CTE mismatch to Si resulting in lower thermally induced stress at the TSV-interface. As test layout a cross-sectioned double-die stack was used consisting of a top die with TSVs which is bonded by Cu-Sn Solid Liquid Interdiffusion Bonding (SLID) to the bottom die. Three different experimental methods have been used to determine mechanical stresses in silicon nearby tungsten TSVs - HR-XRD performed at a synchrotron beamline, microRaman spectroscopy and stress relief techniques put into effect by FIB milling. All methods possess, to a different extend, high spatial resolution capabilities. However they differ in their sensitivity and response to the particular stress tensor components relevant for the residual stress state nearby TSV structures. Stress measurements were performed on test samples with W-TSVs in thinned dies, which were SLID bonded to a thicker Si substrate die. The measurements captured stresses introduced by the W-TSV as well as by the wafer bonding process. A stress range from several MPa to hundreds of MPa could have been covered with a spatial resolution ranging from 100 nm to tens of microns. Measurement results were compared to one another and to simulated stresses from finite element analysis (FEA). All experimental methods show the influence of W and Cu-Sn-Bond in Si. The very high stress sensitivity for HR-XRD below 1 MPa could be shown. For small stress gradients the analysis of the peak position gives reasonable results and for larger stress gradients a profile analysis of the diffraction peak is more accurate. The results show that in intrinsic stress in W may have to be considered in FEA and more attention should be directed to the accuracy of the FE-modelled Cu-Sn SLID bond with resp- ct to shrinkage during phase formation of Cu3Sn

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“…High stress in gate electrode films can limit the thickness of the metal film as the force per unit width is enhanced with increasing thickness. (Figure 1 1) [30]. This thickness limitation could further compromise gate resistance requirements.…”

Section: Thermal Chemical and Mechanical Stabilitymentioning

confidence: 94%

Metal gates for advanced CMOS technology

Maiti

Tobin

1999

SPIE Proceedings

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This paper will provide an overview of the emerging trends in metal gate solutions for advanced CMOS technology. Performance enhancement in silicon-based CMOS technology through MOSFET scaling has shown some limitations with the current polysilicon gate electrode. Replacing polysilicon gate electrode by metal appears to be promising. However, the choice of the metal gate material depends on its work function (single or dual metal gates), thermal/chemical stability with surrounding materials, process integration (conventional or inlaid approach), deposition process, resistivity, and eventually performance, reliability and future scaling. This paper will discuss some of the results published in the literature that address some of these issues and propose future directions. Single mid-gap metal gate approach appears to be simpler from an integration point of view but achieving low MOSFET threshold voltage is a concern. Some channel engineering approaches have been reported to address this issue. Dual metal gate approach with work function similar to n and p doped poly-Si appears ideal, although processing complexity could be a hindrance. Also the need for inlaid gate integration could be enhanced because of thermal/chemical stability effects of metal gate electrode with underlying gate dielectric, the inability to etch new materials or to reduce device instability due to film stress as in the conventional approach. The performance improvement of CMOS devices has been estimated with metal gates along with reliability issues.

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The evolution of growth stresses in chemical vapor deposited tungsten films studied by in situ wafer curvature measurements

Cited by 27 publications

References 36 publications

Gate MOSCAP Studies on Electroless Deposited Nickel Boron as Word Line Candidate Metal for Future Scaled 3-D NAND Flash

Gate MOSCAP Studies on Electroless Deposited Nickel Boron as Word Line Candidate Metal for Future Scaled 3-D NAND Flash

Residual stress investigations at TSVs in 3D micro structures by HR-XRD, Raman spectroscopy and fibDAC

Metal gates for advanced CMOS technology

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