1979
DOI: 10.1149/1.2128981
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The Evolution of Silicon Semiconductor Technology: 1952–1977

Abstract: not Available.

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1979
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Cited by 28 publications
(17 citation statements)
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“…The silicon dioxide grown at 950 -1000°C and 3000 -7000A thick provides the junction diffusion mask and edge protection. Unlike the epoxy-silicon interface of the surface barrier detector, the properites of this silicon-silicon dioxide interface are fairly well understood [6]. The n+ and p+ contacts are diffused 0.2 -0.5pm deep (typically at 900 -950°C, 10-30 minutes) into the wafer and consequently are much more rugged than the metal contacts on the surface barrier detectors.…”
Section: Diffused Junction Detectorsmentioning
confidence: 99%
“…The silicon dioxide grown at 950 -1000°C and 3000 -7000A thick provides the junction diffusion mask and edge protection. Unlike the epoxy-silicon interface of the surface barrier detector, the properites of this silicon-silicon dioxide interface are fairly well understood [6]. The n+ and p+ contacts are diffused 0.2 -0.5pm deep (typically at 900 -950°C, 10-30 minutes) into the wafer and consequently are much more rugged than the metal contacts on the surface barrier detectors.…”
Section: Diffused Junction Detectorsmentioning
confidence: 99%
“…The first transistor was invented in 1947 by Bardeen, Brattain, and Shockley at Bell Labs (Bardeen & Brattain, 1948). Since its invention, there have been numerous changes over the years with the field-effect transistor (FET) taking the forefront (Deal & Early, 1979;Chih-Tang, 1988). The development of complementary metal-oxide semiconductor (CMOS) technology (consisting of PMOS and NMOS; P for p-type and N for n-type, indicating the type of dopants used for the source-drain contacts) with individual FETs as either PMOS or NMOS is the current basis for chipsets used in digital integrated circuits (ICs) (Weste & Eshraghian, 1985).…”
Section: Introductionmentioning
confidence: 99%
“…In effect, as the FET size scaled, parasitic capacitance between the contacts and gate became a major issue which led to new designs and materials to be used (Bohr, 2011). A paradigm shift occurred in 2000 with the introduction of the three-dimensional (3D) finFET technology by Dr. Chenming Hu (Hisamoto et al, 2000). The 3D structure with the fin protruding out and the gate wrapped around three sides allowed better control of the channel current during on/off state and also overcame the problem of drain-induced barrier lowering, which was responsible for large off-state leakage currents due to the small channel size.…”
Section: Introductionmentioning
confidence: 99%
“…The semiconductor industry has used 'conventional' top-down approaches -photo and scanning beam lithographies, for example -to manufacture microelectronic devices at an enormous scale [13][14][15]. The essential elements of photolithographic patterning are illustrated schematically in Fig.…”
Section: Introductionmentioning
confidence: 99%