The Failure Mechanism of Gate Resistance Testing for Power MOSFET

Abstract

The vertical DMOS (Double Diffused MOSFET) is widely used in power microelectronics, its switching performance is determined mainly by the gate resistance and the input capacitance. Thus a gate resistance testing technique is developed in order to determine its device functionality. In this paper we will discuss various processes induced device failures, such as the poor interconnect of the poly gate and the metal, the bonding wire, and the etch process, and their impact to the performance and reliability of the devices as well as the in-line testing method used for the performance validation. IntroductionPower MOSFET is widely used now as a switching power supply device for appliance, computer, automotive and other application. Today the vertical structure DMOS in both planar and trench structures [1] have good performance with low conduction resistance RDS(on) which determines the power dissipation of themselves, and with the optimization in the process and package technology for their switching speed and ruggedness for operating in extreme electrical and thermal conditions. The switching speed depends on the parameter of gate charge and the ruggedness for electrical and thermal stress depends on the breakdown voltage of the device. In fact the switching speed, the conduction resistance and the ruggedness performance need to consider in the same time in order to estimate the tradeoffs and performance optimization from the point of process technology and package technology.For power MOSFET now switching speed is determined mainly by the gate charge that a device needs to turn on itself [3]. So the time required to turn on and turn off depends on the charge and discharge process of the device, this is determined by the time constant RG*CG. So increasing switching speed with constant gate charge is necessary to reduce the gate resistance and input capacitance.In order to characterize the device's switching performance, the gate resistance testing is performed. From the testing result, the devices with poor switching performance can be screened out, and from the failure analysis, the processing induced defects can also be investigated to improve the device's yield and reliability.