Articles you may be interested inConduction processes in metal-insulator-metal diodes with Ta2O5 and Nb2O5 insulators deposited by atomic layer deposition J. Vac. Sci. Technol. A 32, 01A122 (2014); 10.1116/1.4843555 Perimeter and area current components in HfO2 and HfO2−x metal-insulator-metal capacitors J. Vac. Sci. Technol. B 31, 01A117 (2013); 10.1116/1.4774104 Reliability studies on Ta 2 O 5 high-κ dielectric metal-insulator-metal capacitors prepared by wet anodizationHigh-temperature ͑ϳ90-150°C͒ conduction mechanisms of metal-insulator-metal ͑MIM͒ capacitors with atomic-layer-deposited HfO 2 dielectric are studied. In the low field range, the Schottky emission current is dominant, and the deduced dielectric constant is close to the static one of HfO 2 . In the high field range, the resulting leakage current complies with the Poole-Frenkel ͑PF͒ emission, which is demonstrated by the fact that the extracted dielectric constant equals the optical frequency one ͑i.e., square of refractive index͒ of HfO 2 . The underlying mechanisms are discussed based on carrier velocities under different electric fields. Further, the deduced Schottky barrier height is ϳ0.251-0.274 eV in the low field range, which relates to the contributions from high density traps in the HfO 2 film and the nonideal TaN/ HfO 2 interface, etc. The extracted trap potential well depth for the PF effect is ϳ1.11-1.37 eV in the high field range.

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Heel crack is one of the most complicated reliability problems of wire bonding in the power electronic package. In this work, we investigate the effects of solder IR reflow to the heel crack both in experimental and FEA simulation study for the 2-5mil (diameter) aluminum wire. The results show that the plastic strain at the heel region induced by the wire bonding process, influence of molding process and the coefficient of thermal expansion (CTE) mismatches between different components in package are the main causes of heel crack happened in IR reflow. With respect to the trend of lead free, the simulation is also processed under the three temperature hierarchies with different peak reflow temperature (220X, 240X, 260X) and wetting time. From von mises stress and related plastic strain distributions, it can been seen that, during the reflow, the heel region of the wire is endured larger stress and plastic strain than other areas, and with the peak reflow temperature and wetting time increasing, the plastic strain also increases about 20%, which is very critical for material fatigue.

The vertical DMOS (Double Diffused MOSFET) is widely used in power microelectronics, its switching performance is determined mainly by the gate resistance and the input capacitance. Thus a gate resistance testing technique is developed in order to determine its device functionality. In this paper we will discuss various processes induced device failures, such as the poor interconnect of the poly gate and the metal, the bonding wire, and the etch process, and their impact to the performance and reliability of the devices as well as the in-line testing method used for the performance validation. IntroductionPower MOSFET is widely used now as a switching power supply device for appliance, computer, automotive and other application. Today the vertical structure DMOS in both planar and trench structures [1] have good performance with low conduction resistance RDS(on) which determines the power dissipation of themselves, and with the optimization in the process and package technology for their switching speed and ruggedness for operating in extreme electrical and thermal conditions. The switching speed depends on the parameter of gate charge and the ruggedness for electrical and thermal stress depends on the breakdown voltage of the device. In fact the switching speed, the conduction resistance and the ruggedness performance need to consider in the same time in order to estimate the tradeoffs and performance optimization from the point of process technology and package technology.For power MOSFET now switching speed is determined mainly by the gate charge that a device needs to turn on itself [3]. So the time required to turn on and turn off depends on the charge and discharge process of the device, this is determined by the time constant RG*CG. So increasing switching speed with constant gate charge is necessary to reduce the gate resistance and input capacitance.In order to characterize the device's switching performance, the gate resistance testing is performed. From the testing result, the devices with poor switching performance can be screened out, and from the failure analysis, the processing induced defects can also be investigated to improve the device's yield and reliability.