The Failure Mechanism Worst Stress Condition for Hot Carrier Injection of NMOS

Abstract

Various voltage bias and temperature stress conditions are adopted for hot carrier injection (HCI) test by not only the different device type (N or PMOS) but also the different technology with various device feature sizes (such as W/L=10/0.28µm and 10/0.1µm). Due to different dominant mechanism for hot carrier generation and performance degradation corresponding to various devices, the appropriate stress condition selection is crucial to address the HCI lifetime for device. Based on the conditions that may occur in real application and according to the experimental data, this work discussed the worst stress condition including the voltage and temperature for NMOS device with specific device feature size. Theoretical explanation is presented for each case. An HCI stress condition guideline is summarized in the end.

Fabrication Variability in Multiple Gate MOSFETs: A Bulk FinFET Study

“…The measurement was done by randomly se- results have been shown in variation-aware VLSI design 13,14 with a non-Gaussian distribution. The bump of tail with non-Gaussian distribution implies a non-ideal factor influencing transistors performance, such as hot carrier, 15 Poole-Frenkel effect, 16 high field degradation, etc. The short channel devices with channel length of 60 nm show a mean DIBL value (μDIBL) of 549.98 mV/V and standard deviation (σDIBL) of 429.24 mV/V.…”

Investigations of hot carrier injection on NMOSFET with high Vds and low Vgs stress

“…Hot hole injection into the gate oxide near the drain by this electric field. This injection leads to hot-holes injection into oxide and positive-charged traps are thus generated [4] . To further confirm the correlation of hole injection with the electric field, different Vds were forced on the drain, with Vg forced at 0.62V.…”

“…The worst stress temperature also changes from RT to high temperature. The e-e scattering mechanism is used to interpret this trend [4] . To reduce hot carrier injection of a MOSFET, LDD has been implemented to meet a tradeoff between performance and hot electron injection [5,6,10] .…”

The impact of self-heating and its implications on hot-carrier degradation – A modeling study

“…The commonly accepted picture is that HCD in long-channel devices becomes weaker at elevated temperatures because device heating accelerates scattering mechanisms, which typically suppress the high-energy part of the carrier ensemble and hence weaken HCD [8,9] In contrast to that, in scaled devices HCD was reported to be enhanced at higher temperatures [10][11][12][13]. A possible explanation for this change of the temperature behavior (which was suggested to occur at channel lengths less than ∼100 nm) is that in scaled devices carrier-carrier interactions become the dominant scattering mechanism, while other scattering mechanisms are suppressed [14,15]. Carrier-carrier interactions are considered to populate the high energetic tail of the carrier spectrum [14,[16][17][18][19] -i.e., accelerate HCD -and the rate of this process is an increasing function of T .…”