The FLYSIG prototyping approach

Abstract

In 1 this paper we presents a customized approach to rapid prototyping based on a new chip design. The chip is named FLYSIG 2 and adapts the prototyping architecture to the target architecture and the application domain in view. The chip architecture is scalable according to the requirements of arithmetic operators and interconnection flexibility. The prototyping chip is configurable in terms of operator functionality and operator interconnection. A FL-YSIG prototyping chip with 720 add / sub operators has been already been designed and a smaller version is just running through the fab. The design process of FLYSIG based rapid prototyping is supported by tools providing automated scheduling, performance analysis and code generation. The FLYSIG prototyping approach is illustrated by an example of reasonable complexity, i.e. a nested loop convolution algorithm which could be prototyped with the FLYSIG approach easily.