The fundamental downscaling limit of field effect transistors

Abstract

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.

Recent Progress on Reversible Quantum-Flux-Parametron for Superconductor Reversible Computing

“…The switching energy (energy dissipation per switching event) of a single CMOS gate is expected to reach 100 k B T , where k B is the Boltzmann's constant and T is temperature, by reducing the feature size to approximately 5 nm [1]. However, since 100 k B T switching energy is a thermal limit for normal (non-adiabatic) CMOS logic [1], [2], it is not practical to achieve even smaller switching energy via device miniaturization. One possible solution to go beyond this limit is to adopt reversible computing [3], [4].…”

Two-Dimensional MX2 Semiconductors for Sub-5 nm Junctionless Field Effect Transistors

“…Unavoidable problems arise, such as heat dissipation and quantum effects, etc. [ 5 , 6 ] The channel materials are crucial to enable high-performance device designs. It was shown that 5-nm will be the limit of channel length in field effect transistors (FETs) based on Si [ 6 ].…”

“…[ 5 , 6 ] The channel materials are crucial to enable high-performance device designs. It was shown that 5-nm will be the limit of channel length in field effect transistors (FETs) based on Si [ 6 ]. Among the many possible candidates as suggested in the ITRS [ 4 ], 2D materials are the mostly likely to be used in next-generation transistors [ 7 , 8 ] due to their ultimate thickness providing excellent gate control and their dangle bond–free surfaces preventing additional inelastic electron scattering.…”

Ultrafast Strong Field Dynamics in Dielectrics

“…It is necessary to consider the non zero probability of electrons tunneling through the energetically forbidden regions between the individual transistors. This makes the performance of the electronic device unreliable and unstable [14].…”