A method is presented for quantum-mechanical ballistic transport calculations of realistic two-and threedimensional open devices that may have any shape and any number of leads. Observables of the open system can be calculated with an effort comparable to a single calculation of a suitably defined closed system. The method is based on a previously developed scheme for calculating transmission functions, the contact block reduction method, and is shown to be applicable to the density matrix, the density of states, and the local carrier density. The electronic system may be characterized by a single or multiband Hamiltonian. We illustrate the method for the four-band GaAs hole transport through a two-dimensional three-terminal T-junction device and for the electron tunneling through a three-dimensional InAs quantum dot molecule embedded into an InP heterostructure.

We present an efficient method to calculate the ballistic transmission function and current of an arbitrarily shaped, multiterminal two- or three-dimensional open device. It is shown that the calculation of the energy dependent transmission function can be reduced to a single calculation of some stationary states of the isolated device and the inversion of a small matrix that is energy dependent. The size of this matrix is shown to be governed by the size of the boundary region between the leads and the device. The method that we term contact block reduction method is illustrated by a numerical example.

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We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.

We present a self-consistent one-dimensional (1D) quantum transport simulator based on the Contact Block Reduction (CBR) method, aiming for very fast and robust transport simulation of 1D quantum devices. Applying the general CBR approach to 1D open systems results in a set of very simple equations that are derived and given in detail for the first time. The charge self-consistency of the coupled CBR-Poisson equations is achieved by using the predictor-corrector iteration scheme with the optional Anderson acceleration. In addition, we introduce a new way to convert an equilibrium electrostatic barrier potential calculated from an external simulator to an effective doping profile, which is then used by the CBR-Poisson code for transport simulation of the barrier under non-zero biases. The code has been applied to simulate the quantum transport in a double barrier structure and across a tunnel barrier in a silicon double quantum dot. Extremely fast self-consistent 1D simulations of the differential conductance across a tunnel barrier in the quantum dot show better qualitative agreement with experiment than non-self-consistent simulations.