The GBT-SCA, a radiation tolerant ASIC for detector control and monitoring applications in HEP experiments

Abstract

The future upgrades of the LHC experiments will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these needs, the GBT (Giga-Bit Transceiver optical link [1,2]) architecture was developed to provide the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data. The GBT-SCA ASIC, part of the GBT chip-set, has the purpose to distribute control and monitoring signals to the on-detector front-end electronics and perform monitoring operations of detector environmental parameters. In order to meet the requirements of different front-end ASICs used in the experiments, it provides various user-configurable interfaces capable to perform simultaneous operations. It is designed employing radiation tolerant design techniques to ensure robustness against SEUs and TID radiation effects and is implemented in a commercial 130 nm CMOS technology. This work presents the GBT-SCA architecture, the ASIC interfaces, the data transfer protocol, and its integration with the GBT optical link.

FELIX: the New Detector Interface for the ATLAS Experiment

“…The dataflow to and from the front-ends has been demonstrated. FELIX can also trigger a front-end test pulse from a test application, and successfully configure ASICs and FPGAs via the GBT-SCA's GPIO, I 2 C, SPI and JTAG interfaces [16]. Other highlights also include the ability to read out ADC monitoring data and configure the GBTx on the L1DDC board [17].…”

“…10. GBT-SCA chips are used to control the power rails, I 2 C buses and also perform on-board temperature measurement [16]. Besides the interface to EC links with the GBT-SCA chip, each GBTx on the LTDB provides the recovered 40 MHz TTC clock from a FELIX GBT link to the ASICs of the NEVIS ADC and serializers LOCx2, and also sends the BCR (Bunch Counter Reset) signal to the LOCx2 ASIC [18] [19].…”

FELIX: The new detector readout system for the ATLAS experiment

“…FELIX firmware modules and connectivity frame at 40.08 MHz, however the actual user bandwidth is 3.2 Gb/s since the payload length is 80 bits. The remaining 40 bits are reserved for the forward error correction, a frame identifier and the slow control for GBTx ASIC [14] and GBT-SCA [15]. The data frames are encoded/decoded in the GBT logic block and split into 20 bits at 240.48 MHz for input to the GTH interface.…”

The New Version of the LHCb SOL40-SCA Core to Drive Front-End GBT-SCAs for the LHCb Upgrade

“…In view of this requirement, the experiment is using the GBT chipset [2] and its related components developed by the EP-ESE group at CERN, for data readout as well as for fast control and slow control tasks. Furthermore, to aid the slow control tasks, the GBT-SCA ASIC [3] is widely used to configure and monitor the Front-End electronics (FE) via a set of protocols such as JTAG, I2C and SPI. In LHCb, all the chips located the FE are controlled via FPGA-based electronics boards -interfaced to the software control system via a PCIe bus -with bidirectional optical links through the optical capabilities of the GBT chipset.…”