The Hardware Thread Interface Design and Adaptation on Dynamically Reconfigurable SoC

Wang, Ying; Weinan, Chen; Wang, Xiaowei; You, Hongjun; Peng, Chenglian

doi:10.1109/icess.2009.56

Cited by 3 publications

(5 citation statements)

References 8 publications

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“…The well known concept of software thread, similar as the POSIX model [3], can be applied and shift the paradigm HW thread, providing a unified transparent model [3]. The coexistence of a hybrid, software and hardware model in an operating system environment, raises concerns namely regarding an unified programming model, portability, legacy software support, suitable interface and synchronization mechanisms, communication overhead and resource optimization [4], [5], [6], eventually exacerbated in resource constrained embedded contexts. As an example of an unified hardware/software thread programming model, [4], [5], show some of the benefis of this methodology.…”

Section: Related Workmentioning

confidence: 99%

“…The coexistence of a hybrid, software and hardware model in an operating system environment, raises concerns namely regarding an unified programming model, portability, legacy software support, suitable interface and synchronization mechanisms, communication overhead and resource optimization [4], [5], [6], eventually exacerbated in resource constrained embedded contexts. As an example of an unified hardware/software thread programming model, [4], [5], show some of the benefis of this methodology. Communication overhead on a shared bus, and resource utilization are maintained low in both cases, while still offering performance improvements.…”

Section: Related Workmentioning

confidence: 99%

“…Communication overhead on a shared bus, and resource utilization are maintained low in both cases, while still offering performance improvements. [5], [7] , [6] also argue on the importance of a hardware/software transparent model and homogenous interfaces, in order to achieve suitable HW abstraction and legacy-software reutilization.…”

Section: Related Workmentioning

confidence: 99%

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Co-Designed FreeRTOS Deployed on FPGA

Pereira

Oliveira

Pinto

et al. 2014

2014 Brazilian Symposium on Computing Systems Engineering

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Most embedded systems are bound to real-time constraints. Two of the critical metrics presented in these systems are determinism and latency. Due to growing in complexity of embedded applications, real time operating systems (RTOS) are needed, not only to hide the increasingly complex hardware, but also to provide services to the system's running tasks. Unfortunately, this new layer on an embedded system puts more pressure on the aforementioned metrics. One of the ways to cope with this problem is to offload RTOS run-time services to the hardware layer.This paper presents a hybrid hardware/software implementation of this technique upon the well known FreeRTOS, improving system's latency and predictability, by migrating critical runtime services to hardware. The developed hardware accelerators were synthesized on a field-programmable gate array (FPGA), exploiting the point-to-point bus Fast Simplex Link (FSL) to interconnect to the Xilinx's Microbaze soft-core processor.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Co-Designed FreeRTOS Deployed on FPGA

Pereira

Oliveira

Pinto

et al. 2014

2014 Brazilian Symposium on Computing Systems Engineering

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“…Therefore, this protocol software can be reused with only the other half of the interfaces being unique (e.g., Internet). Another reuse possibility is the threads (a set of operations executed in sequence [12]) of software logic that exists in systems [40]. These software design artifacts can be reused in any number of substations comprising the smart grid.…”

Section: Customer-smart Grid Interactionmentioning

confidence: 99%

Representativeness models of systems: smart grid example

Schneidewind

2011

Innovations Syst Softw Eng

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Given the great emphasis being placed on energy efficiency in contemporary society, in which the smart grid plays a prominent role, this is an opportune time to explore methodologies for appropriately representing system attributes. We suggest this is important for effective system development because the primary factor in correctly mapping between requirements and implementation is how representative the system design is of requirements. Since representativeness is an abstract term, it is imperative to identify ways to quantify it. We use several metrics. Among these is the priority of system elements (e.g., electric generator) in the set of elements, based on importance to system success. Secondly, fault tree analysis is employed to identify elements that operate in an unsafe state and the probabilities of reaching these unsafe states. Thirdly, state transition analysis provides traces of which elements are on the routes to unsafe states. These analyses provide the information needed to reduce element faults and failures on a priority basis.

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“…This approach is pursued in ReconOS [2], where the hardware threads and a system call API, both described in VHDL, are proposed to make the programming process easier. In all these cases, as well as in SHUMDR [3], the thread is composed at least by a finite state machine to sequentially control the accelerator execution.…”

Section: Introductionmentioning

confidence: 99%

Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow

Gantel

Benkhelifa

Lemonnier

et al. 2012

2012 International Conference on Reconfigurable Computing and FPGAs

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Heterogeneous Reconfigurable Systems-on-Chip (HRSoC) contain as their name suggests, heterogeneous processing elements in a single chip. Namely, several processors, hardware accelerators as well as communication networks between all these components. In order to leverage the programming complexity of this kind of platform, applications are described with software threads, running on processors, and hardware threads, running on FPGA partitions. Combining techniques such as dynamic and partial reconfiguration and partial readback with the knowledge of the bitstream structure offer the ability to target several partitions using a unique configuration file. Such a feature permits to save critical memory resources. In this article, we propose to tackle the issue of designing fully independent partitions, and especially to avoid the routing conflicts which can occur when using the standard Xilinx FPGA design flow. To achieve the relocation process successfully, we propose a new design flow dedicated to the module relocation, using the standard tools and based on the Isolation Design Flow (IDF), a special flow provided by Xilinx for secure FPGA applications.

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The Hardware Thread Interface Design and Adaptation on Dynamically Reconfigurable SoC

Cited by 3 publications

References 8 publications

Co-Designed FreeRTOS Deployed on FPGA

Co-Designed FreeRTOS Deployed on FPGA

Representativeness models of systems: smart grid example

Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow

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