The Impact of Fin Number on Device Performance and Reliability for Multi-Fin Tri-Gate n- and p-Type FinFET

Yeh, Wen–Kuan; Zhang, Wenqi; Chen, Haw‐Wen; Yang, Yi-Lin

doi:10.1109/tdmr.2018.2866800

Cited by 39 publications

(17 citation statements)

References 11 publications

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“…The TCAD calibrated part of the device with experimental data 13 observed that the I ON is highest for HfO 2 , followed by Si 3 N 4 spacer, and least for Air spacer. The hybrid spacer shows higher I ON compared to Air spacer due to the presence of Si 3 N 4 in fin extension which enhances carrier densities.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…In multi-fin structures, multiple parallel fins between source and drain increase the total channel width. 13,14 Along with these problems, FinFETs possess some other process challenges in terms of minimal uniformity between fin shapes, gate buckling, fin bottom erosion, lower I ON due to higher quantum mechanical effects with reduced channel area, and higher aspect ratio problems (F H /F W ). All the FinFET configurations like a double gate, tri-gate, pie-gate FinFET, omega FinFET, and a single taller fin, increase the fabrication difficulties.…”

Section: Introductionmentioning

confidence: 99%

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Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Sreenivasulu

Narendar

2021

Int J RF Mic Comp-Aid Eng

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Multi-fin devices are the most reliable option for terahertz (THz) frequency applications at nano-regime. In this work impact of spacer engineering on multi-fin SOI FET performance is evaluated by invoking single low-k (Air), high-k (Si 3 N 4 , HfO 2 ), and hybrid dual-k (Air + Si 3 N 4 ) spacer in the underlap section at nano-regime. The simulation study reveals that the high-k (HfO 2 ) spacer gives a higher switching ratio (I ON /I OFF ) in the order of ~10 7 , subthreshold swing (SS) = 72 mV/dec, drain induced barrier lowering (DIBL) = 22.14 mV/V and quality factor (Q) = g m /SS = 0.16 μS-dec/mV. Furthermore, to measure the suitability of the device for high frequency applications various analog/RF parameters are studied. The high-k (HfO 2 ) spacer dominates DC and analog performance, whereas the low-k (Air) spacer dominates the RF domain with f T = 1.26 THz, GBW = 0.251 THz, TFP = 29 THz range, and with smaller intrinsic delays. Hybrid dual-k spacer (Air + Si 3 N 4 ) outperforms in terms of gain (A V ) and output resistance (R o ). The Air spacer exhibits lower dynamic power of 2.09 aJ/μm and power consumption of 1.04 aJ/μm. The linearity metrics for multi-fin SOI FET parameters like g m2 , g m3 , HD1, HD2, THD, and VIP2 are also studied. The Air spacer followed by hybrid spacer outperforms in linearity, and harmonic distortion components and ensures its potential for RF applications at nano-regime.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Sreenivasulu

Narendar

2021

Int J RF Mic Comp-Aid Eng

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“…They showed that Mc-FET contributes ultra-low I OFF and high I ON which are satisfying low standby power (LSTP) and high performance (HP) applications. Wen-Kuan Yeh et al [29] investigates the effect of carrier quantization on multi-n high K/Metal tri-gate n-type and p-type FinFET where several Fins exhibited superior device performance. Nevertheless, the above research towards M-FinFET is mainly focused on device characteristics without focus on the effects of interface trap charges.…”

Section: Introductionmentioning

confidence: 99%

Effect of positive and negative interface trap charges on the performance of M-FinFET and its RF/linearity analysis

Das

Chowdhury

Chakroborty

et al. 2021

Preprint

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Multiple Fins structured FinFET (M-FinFET) is a promising semiconductor device for future improvisation of CMOS technology. In this paper, we investigate the impact of interface trap charges (positive and negative trap) at the HfO2/Si interface in M-FinFET for the first time. The various important DC attributes, RF/analog, and linearity metrics are studied in presence and absence of traps. Simultaneously, the various trap concentration effect on the characteristics of M-FinFET are also observed. The results show that the introduction of interface trap charges (ITC) has optimized the ON current, OFF current, and also improves sub-threshold swing (SS) characteristics as compared to no trap condition. It is observed that positive trap having trap concentration of 1012/cm2 enhances the ION ~5.14x, SS by 44.75%, and various important RF/analog parameter such as transconductance (Gm) improves by a factor 5, device efficiency by 7.4% and intrinsic gain (Av) 80.4%. On the other hand, linearity parameters like VIP2, VIP3 and 1 dB compression point show better performance in presence of positive and negative trap.

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“…FinFET with multiple fins show promising results in terms of power gain when compared to a single tall fin [13]. Using a metal gate gives better performance in terms of current driving capability.…”

Section: Introductionmentioning

confidence: 99%

Design, Simulation and Analysis of Junction Version Multi-Fin FINFET

Rao

Vandana

2021

Silicon

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This paper presents a 3-D statistical simulation study of Multi-fin junction FinFET for different technology nodes 32nm, 24 nm & 10 nm. For each and every technology node their corresponding Electrical parameters like on current (Ion), off current (Ioff), threshold voltage (Vth) are reported in the paper and also RF/Analog parameters like transconductance (gm), output conductance (gd), intrinsic gain (gm/gd) are reported. And also parameters like Electric field (E), Electron density (ne), Electron mobility (µ) which are measured across the device length are simulated. The proposed structure showed performance improvement in all the parameters when the technology node is decreased.

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The Impact of Fin Number on Device Performance and Reliability for Multi-Fin Tri-Gate n- and p-Type FinFET

Cited by 39 publications

References 11 publications

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Effect of positive and negative interface trap charges on the performance of M-FinFET and its RF/linearity analysis

Design, Simulation and Analysis of Junction Version Multi-Fin FINFET

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