The impact of high-κ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

Cheng, Baolei; Cao, Min; Rao, Rakesh; Inani, A.; Voorde, Paul Vande; Greene, W.; Stork, J.M.C.; Zhang, Yu; Zeitzoff, P.; Woo, J.C.S.

doi:10.1109/16.772508

Cited by 272 publications

(105 citation statements)

References 12 publications

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“…With further scaling, the high-k gate dielectrics and metal gate electrodes will be required for high-performance and low-power CMOS applications. Much work has been done for high-k/metal-gate transistors in [25], [26] recently. In this paper the proposed overshooting model is also applied to the inverter constructed with high-k/metal-gate transistor, where the 32 nm PTM high-k/metal-gate models for highperformance applications (PTM HP) and for low-power ap- plications (PTM LP) [20], [21] are utilized in the SPICE simulation.…”

Section: High-k/metal-gate Modelmentioning

confidence: 99%

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

Huang

Kurokawa

Hashimoto

et al. 2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-With the scaling of complementary metal-oxidesemiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

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Section: High-k/metal-gate Modelmentioning

confidence: 99%

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

Huang

Kurokawa

Hashimoto

et al. 2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…However, the studies illustrated that superseding SiO 2 with high K dielectrics reduces the device performance due to the increased fringing fields from the gate to the source/drain regions, which weakens the control of gate over the channel. The high K and Si system results in unacceptable level of bulk fixed charge, high interface trap density and low silicon interface carrier mobility [17]. Consequently, extremely thin layer of interfacial oxide is used as a coating to reduce the interface trap density thus increasing the device performance [18].…”

Section: Introductionmentioning

confidence: 99%

“…However, the level to which the gate oxide thickness can be scaled down is limited by direct tunneling which leads to an increase in the gate leakage current thus degrading the device performance. It also causes an increase in static power consumption, which can hamper the circuit operation [17]. In order to overcome the above limitations intensive stress has been made for the use of high K dielectrics as a gate insulator in lieu of SiO 2 to prevent direct tunneling leakage current.…”

Section: Introductionmentioning

confidence: 99%

Analytical Modeling and Simulation for Dual Metal Gate Stack Architecture (DMGSA) Cylindrical/Surrounded Gate MOSFET

Ghosh¹,

Haldar²,

Gupta³

et al. 2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A Dual metal gate stack cylindrical/ surrounded gate MOSFET (DMGSA CGT/SGT MOSFET) has been proposed and an analytical model has been developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is demonstrated that incorporation of gate stack along with dual metal gate architecture results in improvement in short channel immunity. It is also examined that for DMGSA CGT/SGT the minimum surface potential in the channel reduces, resulting increase in electron velocity and thereby improving the carrier transport efficiency. Furthermore, the device has been analyzed at different bias point for both single material gate stack architecture (SMGSA) and dual material gate stack architecture (DMGSA) and found that DMGSA has superior characteristics as compared to SMGSA devices. The analytical results obtained from the proposed model agree well with the simulated results obtained from 3D ATLAS Device simulator.Index Terms-Dual metal gate stack architecture (DMGSA), surrounded/cylindrical gate MOSFET (CGT/SGT), short channel effects (SCEs)

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“…16 It was also reported that the stacking of high-k with SiO 2 at channel interface would be helpful in reducing the barrier-lowering effect due to the high-k fringing fields. 17 Therefore, interfacial layer indeed plays an essential role in high-k devices. 18,19 Nevertheless, the study of the application of devices with high-k dielectrics is of interest nowadays.…”

Section: Introductionmentioning

confidence: 99%

Photo-induced tunneling currents in MOS structures with various HfO2/SiO2 stacking dielectrics

Pang

Hwu

2014

AIP Advances

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In this study, the current conduction mechanisms of structures with tandem high-k dielectric in illumination are discussed. Samples of Al/SiO2/Si (S), Al/HfO2/SiO2/Si (H), and Al/3HfO2/SiO2/Si (3H) were examined. The significant observation of electron traps of sample H compares to sample S is found under the double bias capacitance-voltage (C-V) measurements in illumination. Moreover, the photo absorption sensitivity of sample H is higher than S due to the formation of HfO2 dielectric layer, which leads to larger numbers of carriers crowded through the sweep of VG before the domination of tunneling current. Additionally, the HfO2 dielectric layer would block the electrons passing through oxide from valance band, which would result in less electron-hole (e−-h+) pairs recombination effect. Also, it was found that both of the samples S and H show perimeter dependency of positive bias currents due to strong fringing field effect in dark and illumination; while sample 3H shows area dependency of positive bias currents in strong illumination. The non-uniform tunneling current through thin dielectric and through HfO2 stacking layers are importance to MOS(p) tunneling photo diodes.

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The impact of high-κ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

Cited by 272 publications

References 12 publications

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

Analytical Modeling and Simulation for Dual Metal Gate Stack Architecture (DMGSA) Cylindrical/Surrounded Gate MOSFET

Photo-induced tunneling currents in MOS structures with various HfO2/SiO2 stacking dielectrics

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