The Impact of Hysteresis Effect on Device Characteristic and Reliability for Various Fin-Widths Tri-Gate Hf0.5Zr0.5O2 Ferroelectric FinFET

Abstract

In this study, we developed a facilitated ferroelectric high-k/metal-gate n-type FinFET based on Hf0.5Zr0.5O2. We investigated the impact of the hysteresis effect on device characteristics of various fin-widths and the degradation induced by stress on the ferroelectric FinFET (Fe-FinFET). We clarified the electrical characteristics of the device and conducted related reliability inspections. For the Fe-FinFET, the hysteresis behavior of the Hf0.5Zr0.5O2-based gate stack in the Si-fin body is apparent, especially at narrower fin-widths, which affects device performance and reliability under voltage stress. The gate ferroelectric film is worsened after voltage stress with higher impact ionization, resulting in hysteresis degradation and serious induced device performance degradation. It is suggested that the hysteresis degradation is caused by both a shift in polarization of the gate ferroelectric film and generation of interface traps after high-energy carrier stress, which was confirmed by crystal structure inspection.