The impact of mechanical stress control on VLSI fabrication process

Ikeda, Shuji; Hagiwara, Yoshihiko; Miura, Hideo; Ohta, Hiroyuki

doi:10.1109/iedm.1996.553126

Cited by 23 publications

(12 citation statements)

References 3 publications

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“…The mechanisms that occur in the large-die-size chip reliability testing can be identified according to the range of [22]. From (2), the mean stress cycle to failure (MSCTF), , can be expressed as (7) where is the standard gamma function. The acceleration factor is defined as the ratio of the stresses induced by TC operations to those induced by TS operations, accounting for stress cycles, dwell time, and transfer time.…”

Section: Resultsmentioning

confidence: 99%

Reliability of VLSI-level chip assembly for evaluating the development of back-end technologies using a test chip with a top two-level metal structure

Chou

Chen

Liu

et al. 2002

IEEE Trans. Device Mater. Relib.

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This paper investigates the effects of area and location of a chip, the material from which it is encapsulated, the geometry of the test structures, accelerated stressing operations and process technologies on the reliability of a VLSI-level chip assembly by using a 12 mm 12 mm large-die-size test chip with various top two-level metal test structures. The test chip is fabricated in a generic 0.18-m six-level AlCu-HSQ interconnect process and using specific dual-damascene Cu-FSG technology for top two-level metal. The proposed model is applied to analyze the failure distribution and identify the failure mechanism. The experimental results indicate that the mechanical and electrical performance of the assembled test chip, both of which depend strongly on back-end processes, can significantly impact the failure distribution and the failure mechanism in testing of the reliability of the chip assembly.Index Terms-Assembly reliability, CMOS, coefficients of thermal expansion (CTE), dual damascene, FSG, HSQ, intermetal dielectric (IMD), large-die-size chip, silicon in-package (SIP), system-on-chip (SOC), test chip, VLSI.

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Section: Resultsmentioning

confidence: 99%

Reliability of VLSI-level chip assembly for evaluating the development of back-end technologies using a test chip with a top two-level metal structure

Chou

Chen

Liu

et al. 2002

IEEE Trans. Device Mater. Relib.

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show abstract

“…It is well known that process steps and device features, such as field oxidation [16,17], shallow [18] and deep trench [19] formation, can introduce stress in device structures. We therefore again measured the current gain, believing it to be an indication of device stress.…”

Section: Device Characteristicsmentioning

confidence: 99%

Influence of SOI-generated stress on BiCMOS performance

Johansson

Malm

Norström

et al. 2006

Solid-State Electronics

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“…It is well known that dislocations are generated when the mechanical stress exceeds some critical value. The authors have reported that the reduction of mechanical stress in gate polysilicon film is an essential aspect of suppressing Manuscript dislocations at the gate edge [1], [2]. Worsened reliability because of the increase in mechanical stress in the oxide has been reported [3], [4].…”

Section: Introductionmentioning

confidence: 97%

Mechanical stress control in a vlsi-fabrication process: a method for obtaining the relation between stress levels and stress-induced failures

Ikeda¹,

Ohta

Miura

et al. 2003

IEEE Trans. Semicond. Manufact.

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An ideal fabrication process is designed to minimize mechanical stress in semiconductor devices and to improve device reliability. Mechanical stress levels were predicted by in-house simulations supported by a thin-film database. These stress levels were correlated with stress-induced defects by TEM analysis supported by fail bit addressing on matured megabit SRAMs. Amorphous-doped silicon film with various annealing temperatures were used for the gate electrode to change the mechanical stress in devices and to get the direct relationship between predicted stress levels and stress related defects. The authors describe brief guidelines for suppressing dislocations in the small geometry shallow-trench isolation process utilizing this system. Polysilicon thickness in the W-polycide gate electrode is designed to minimize mechanical stress in the gate oxide and to suppress the gate oxide failure in probe and class tests. Moreover, critical stress generates dislocations during post source/drain ion implantation anneal obtained by a ball indentation method. This indicated that lower temperature anneal is effective in suppressing the dislocations. A two-step anneal was introduced to suppress dislocations and to enable higher ion activation.

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The impact of mechanical stress control on VLSI fabrication process

Cited by 23 publications

References 3 publications

Reliability of VLSI-level chip assembly for evaluating the development of back-end technologies using a test chip with a top two-level metal structure

Reliability of VLSI-level chip assembly for evaluating the development of back-end technologies using a test chip with a top two-level metal structure

Influence of SOI-generated stress on BiCMOS performance

Mechanical stress control in a vlsi-fabrication process: a method for obtaining the relation between stress levels and stress-induced failures

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