The Impact of N-Drift Implant on ESD Robustness of High-Voltage NMOS with Embedded SCR Structure in 40-V CMOS Process

Improvement of electrostatic discharge current-handling capability for high-voltage multi-finger nLDMOS devices with self-triggered technique

“…Hence, a low ESD level is a serious issue in high-voltage (HV) ICs. Scaling up the device dimension is the conventional method to increase the ESD level, but it is not always effective for metal-oxide semiconductor fieldeffect transistor ESD devices, especially for the HV LDMOS [3][4][5][6][7][8]. The root cause for the scaling limit of ESD robustness of a large-area or a finger-type clamp is the current crowding effect among fingers, and then inducing inhomogeneous triggering of the parasitic bipolar junction transistor (BJT) to cause the non-uniform turn-on issue [1,3].…”

“…The root cause for the scaling limit of ESD robustness of a large-area or a finger-type clamp is the current crowding effect among fingers, and then inducing inhomogeneous triggering of the parasitic bipolar junction transistor (BJT) to cause the non-uniform turn-on issue [1,3]. To overcome this problem, a novel layout arrangement [3][4][5], a new device structure embedding silicon controlled rectifier [6], the gate-coupled technique [9,10], and the substrate-triggered technique [7,8,11] have been proposed for HV LDMOS. The methods in [3][4][5][6] elevate the ESD robustness without occupying additional chip area, while extra ESD detecting circuits and substrate triggering circuits are needed for gate-coupled or substrate-triggered techniques in [7][8][9][10][11].…”

“…To overcome this problem, a novel layout arrangement [3][4][5], a new device structure embedding silicon controlled rectifier [6], the gate-coupled technique [9,10], and the substrate-triggered technique [7,8,11] have been proposed for HV LDMOS. The methods in [3][4][5][6] elevate the ESD robustness without occupying additional chip area, while extra ESD detecting circuits and substrate triggering circuits are needed for gate-coupled or substrate-triggered techniques in [7][8][9][10][11]. Achieving the goal of high ESD current-handling capability without any extra chip area is of course the most candidate method.…”

“…The approaches in [7,12] for low-voltage (LV) NMOS achieving uniform ESD protection in a multi-finger device give us a clue of how to improve the robustness of HV LDMOS without increasing the chip area in a different way from [3][4][5][6]. In [7], a floating guard ring was used to effectively pump the local substrate current of the protection NMOS, and the gatecoupling technique is also adopted, while [12] introduced a self-substrate-triggered technique by inserting a P+ node in the N+ drain region.…”