The impact of negative-bias-temperature-instability on the carrier generation lifetime of metal-oxynitride-silicon capacitors

Physica Status Solidi (a)

Visalli

Hove

et al. 2012

A combined deep‐level transient spectroscopy (DLTS) and electron spin resonance (ESR) study is performed to identify the electrically active defects at the AlN/Si (111) interface. It is shown that the density of deep‐level states not only depends on the thermal budget of the epitaxial deposition but also on the strain built up during growth and upon cooling to room temperature (RT). At the same time, diffusion of Si into the 200 nm thick AlN layer produces a thin crystalline Si3N4 interfacial layer, identified by transmission electron microscopy (TEM). This gives rise to so‐called dangling bond Pb centres at the Si3N4/Si (111) interface. In addition, a strong evolution of the electrically active defect clusters in the silicon substrate close to the interface has been observed both in DLTS and ESR.

Section: Discussionmentioning

confidence: 67%

Electrically active defects at AlN/Si interface studied by DLTS and ESR

Physica Status Solidi (a)

Visalli

Hove

et al. 2012

“…Of course, we cannot completely neglect the possibility that the near mid-gap peaks are related to so-called "generation transients" in a MOS capacitor, which occur after the application of a pulse from deep depletion into accumulation [13,14]. Minority carrier generation by deep levels at the interface or in the depletion region plus carrier diffusion from the neutral substrate will give rise to a capacitance increase by the build-up of an inversion layer after the pulse.…”

Section: Resultsmentioning

confidence: 97%

Comparison between Si/SiO₂ mid‐gap interface states and deep levels associated with silicon‐oxygen superlattices in p‐type silicon

Jayachandran

Delabie

et al. 2016

Phys. Status Solidi C

In this paper, the deep levels found by deep‐level transient spectroscopy in Si‐O superlattices on p‐type silicon substrates are compared with the band of near mid‐gap hole traps typically observed at the Si/SiO2 interface. In addition, the impact of a post‐deposition Forming Gas Annealing is investigated. A large similarity between the two material systems is reported, which indicates that similar silicon‐oxygen bonds may be responsible for the deep hole traps.(© 2016 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

“…The increase found at and above room temperature may originate from minority carrier generation in the depletion region. 2,14,34,35 The latter response differs from a true electron emission spectrum and is typical for a MOS capacitor, biased in deep depletion. It originates from the minority carrier generation either by thermal Shockley-Read-Hall (SRH) carrier generation by deep levels in the depletion region or by the diffusion of minority carriers (holes) from the neutral region toward the negatively biased gate.…”

Section: Resultsmentioning

confidence: 99%

“…It is shown that both in the zero-dot reference sample and in the Ge QD capacitors, two prominent features are present: a peak in the 150-200 K range which is most likely related to so-called dangling bond P b centers and a peak at or above room temperature, which could be related to the so-called minority carrier generation in a MOS capacitor. 34,35 The main impact of the presence of the Ge QDs is the change in the V FB toward more positive values with increasing QD size and indicating the introduction of negative charge and, secondly, the increase in the counterclockwise hysteresis in the C-V curves between a forward and a reverse bias sweep, which is a fingerprint of more pronounced charge trapping. * Electrochemical Society Fellow.…”

mentioning

confidence: 99%

Deep Level Assessment of n-Type Si/SiO₂Metal-Oxide-Semiconductor Capacitors with Embedded Ge Quantum Dots

Aouassa

Vrielinck

ECS J. Solid State Sci. Technol.

2018

This paper reports on a Deep-Level Transient Spectroscopy (DLTS) study of n-type silicon Metal-Oxide-Semiconductor capacitors with Ge Quantum Dots (QDs) embedded in a SiO 2 gate dielectric. For a zero-dot reference and in capacitors fabricated with a 1, 2 or 3 nm amorphous Ge layer similar spectra have been obtained. They are characterized by a peak at or above room temperature for a bias pulse in depletion and by an electron trap around 200 K, which is shown to be associated with dangling bond acceptor states at the Si/SiO 2 interface. The maximum density of states increases with average Ge QD size, while the average activation energy, corresponding with the peak maximum position shifts to lower values. Although no direct evidence of electron tunneling to the Ge QDs has been found so far, there is a marked impact of their presence on the Capacitance-Voltage characteristics, resulting in an increase in the accumulation capacitance with QD size, a shift of the flatband voltage toward more positive gate bias and a counterclockwise hysteresis, associated with the charging and discharging of QD levels and related Ge traps in the SiO 2 .