2006
DOI: 10.1109/jssc.2005.859894
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The Implementation of a 2-Core, Multi-Threaded Itanium Family Processor

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Cited by 125 publications
(25 citation statements)
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“…Based on the above classification, as the sum of "control circuitry" and "operational circuitry" normally determines the "total cost" of a processor design, an inevitable trade-off between performance, cost, and flexibility arises. Figure 1 shows the Control versus Operational circuitry Ratio (COR) observation of several representative processor implementations estimated from their die photos [1,6,10,12], demonstrating a fairly accurate match between the COR value of each processor category and its well-known flexibility degree: the larger the COR, the higher the degree of flexibility. As the same trade off between performance and flexibility will inevitably occur also for any design choices taken by in-vehicle vision processors, the design of an in-vehicle vision processor is usually an optimizing search process of a compromised combination of performance and flexibility fulfillment under the severe in-vehicle cost constraints, such as consuming less than 2 W of power while hopefully achieves several hundreds of GOPS performance against as many vision applications as possible.…”
Section: Introductionmentioning
confidence: 90%
“…Based on the above classification, as the sum of "control circuitry" and "operational circuitry" normally determines the "total cost" of a processor design, an inevitable trade-off between performance, cost, and flexibility arises. Figure 1 shows the Control versus Operational circuitry Ratio (COR) observation of several representative processor implementations estimated from their die photos [1,6,10,12], demonstrating a fairly accurate match between the COR value of each processor category and its well-known flexibility degree: the larger the COR, the higher the degree of flexibility. As the same trade off between performance and flexibility will inevitably occur also for any design choices taken by in-vehicle vision processors, the design of an in-vehicle vision processor is usually an optimizing search process of a compromised combination of performance and flexibility fulfillment under the severe in-vehicle cost constraints, such as consuming less than 2 W of power while hopefully achieves several hundreds of GOPS performance against as many vision applications as possible.…”
Section: Introductionmentioning
confidence: 90%
“…PLL clocks are modified to generate test clocks, which consist of scan clocks and release-capture clocks. The release-capture clock timings are shortened using the ODCS (On-Die ClockShrink) method [12][13] without changing PLL frequency. "Delay Monitor IP" includes embedded ring oscillators (RO), which are customized for DART.…”
Section: T(testcoverage)mentioning
confidence: 99%
“…6 [6,10,15,16]. The coarse grain two-core Itanium [16] contains large wide-issue processors each close to 300 mm 2 in 90 nm technology, while the fine grain AsAP contains single-issue processors less than 1 mm 2 in 0.18 μm technology. Size differences of factors of tens and hundreds make strong impacts on system behavior.…”
Section: Analysis Of the Key Featuresmentioning
confidence: 99%
“…Most chip multiprocessors target a broad range of applications, and each processor in such systems normally contains powerful computational resourcessuch as large memories, wide issue processors [16], and powerful inter-processor communication [10]-to support widely varying requirements. Extra computational resources can enable systems to provide high performance to a diverse set of applications, but they reduce energy efficiency for tasks that can not make use of those specialized resources.…”
Section: Analysis Of the Key Featuresmentioning
confidence: 99%