The Improvement of High-$k$/Metal Gate pMOSFET Performance and Reliability Using Optimized Si Cap/SiGe Channel Structure

Yeh, Wen–Kuan; Chen, Yuting; Huang, Fon-Shan; Hsu, Chia‐Wei; Chen, Chun-Yu; Fang, Yean–Kuen; Gan, Kwang–Jow; Chen, Haw‐Wen

doi:10.1109/tdmr.2010.2065806

Cited by 17 publications

(3 citation statements)

References 11 publications

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“…A tensile strain within the Si capping can also depend on its thickness [29]. An optimal Si cap/SiGe thickness ratio of 0.9 was thus found from [5].…”

Section: Discussionmentioning

confidence: 86%

Performance Dependence on Width-to-Length Ratio of Si Cap/SiGe Channel MOSFETs

Chang

Lin

2013

IEEE Trans. Electron Devices

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This paper measures the n-and p-MOSFETs fabricated through 65-nm high-k/metal gate CMOSFET process flow. The [110] channels of the Si cap on SiGe with different width (W ) and length (L) ratios were compared with Si-only channels. The results show that a high W-L ratio in the [110] n-channel can alleviate the degradation of biaxial compressive stress. Meanwhile, a low W-L ratio in the p-channel can improve the performance; however, the ratio should at least be below two in this paper. The dominance of the longitudinal or transverse configurations successfully explains this phenomenon because of the reliance of the different levels of piezoresistance coefficient on the channel orientation. The threshold voltage shifts versus the W-L ratio in the p-channel is in agreement with the result. The result is verified by a quantitative current comparison at a high bias in the n-/p-channels between the strained SiGe and Si-only channels, which shows that an extreme W-L ratio in the original biaxially strained SiGe channel can result in longitudinal or transverse strain, thereby leading to different levels of performance degradation/improvement.

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“…A tensile strain within the Si capping can also depend on its thickness [29]. An optimal Si cap/SiGe thickness ratio of 0.9 was thus found from [5].…”

Section: Discussionmentioning

confidence: 86%

Performance Dependence on Width-to-Length Ratio of Si Cap/SiGe Channel MOSFETs

Chang

Lin

2013

IEEE Trans. Electron Devices

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“…To control the interface quality, many methods have been extensively explored, such as plasma (N 2 or NH 3 ) nitridation passivation [ 4 , 5 ], sulfur passivation [ 6 ], thermal oxidation [ 7 , 8 ], low-temperature ozone passivation [ 9 , 10 , 11 , 12 ] and Si-cap passivation [ 13 ]. Among them, low-temperature ozone passivation with low thermal budge and Si-cap passivation with excellent properties of interface are considered the most promising passivation methods.…”

Section: Introductionmentioning

confidence: 99%

Investigate on the Mechanism of HfO2/Si0.7Ge0.3 Interface Passivation Based on Low-Temperature Ozone Oxidation and Si-Cap Methods

Yao

Wang

et al. 2021

Nanomaterials

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The interface passivation of the HfO2/Si0.7Ge0.3 stack is systematically investigated based on low-temperature ozone oxidation and Si-cap methods. Compared with the Al2O3/Si0.7Ge0.3 stack, the dispersive feature and interface state density (Dit) of the HfO2/Si0.7Ge0.3 stack MOS (Metal-Oxide-Semiconductor) capacitor under ozone direct oxidation (pre-O sample) increases obviously. This is because the tiny amounts of GeOx in the formed interlayer (IL) oxide layer are more likely to diffuse into HfO2 and cause the HfO2/Si0.7Ge0.3 interface to deteriorate. Moreover, a post-HfO2-deposition (post-O) ozone indirect oxidation is proposed for the HfO2/Si0.7Ge0.3 stack; it is found that compared with pre-O sample, the Dit of the post-O sample decreases by about 50% due to less GeOx available in the IL layer. This is because the amount of oxygen atoms reaching the interface of HfO2/Si0.7Ge0.3 decreases and the thickness of IL in the post-O sample also decreases. To further reduce the Dit of the HfO2/Si0.7Ge0.3 interface, a Si-cap passivation with the optimal thickness of 1 nm is developed and an excellent HfO2/Si0.7Ge0.3 interface with Dit of 1.53 × 1011 eV−1cm−2 @ E−Ev = 0.36 eV is attained. After detailed analysis of the chemical structure of the HfO2/IL/Si-cap/Si0.7Ge0.3 using X-ray photoelectron spectroscopy (XPS), it is confirmed that the excellent HfO2/Si0.7Ge0.3 interface is realized by preventing the formation of Hf-silicate/Hf-germanate and Si oxide originating from the reaction between HfO2 and Si0.7Ge0.3 substrate.

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“…The SiGe channel is one of the most promising candidates as a performance booster for pMOSFETs because of its high hole mobility and compatibility with conventional CMOS processes. [6][7][8][9][10] Negativebias temperature instability (NBTI) is considered to be a major reliability issue for scaled CMOS technologies due to the increased oxide electric field (E ox ) caused by scaled electrical oxide thickness (EOT). Many investigations on the NBTI of SiGe pMOSFETs have focused on degradation characteristics, [11][12][13][14] but under real operating conditions, the devices would be subjected to repeated stress and recovery phases.…”

Section: Introductionmentioning

confidence: 99%

Improved Degradation and Recovery Characteristics of SiGe p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors under Negative-Bias Temperature Stress

Choi

Sohn

Sagong

et al. 2013

Jpn. J. Appl. Phys.

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This paper describes the degradation and recovery characteristics of SiGe pMOSFETs with a high-k/metal gate stack under negative-bias temperature instability (NBTI) stress. The threshold voltage instability (ΔV th) of SiGe pMOSFETs shows an increased percentage of recovery (R) as well as lower degradation than those of control Si pMOSFETs. It is found that the recovery characteristics of SiGe and Si pMOSFETs have similar dependencies on various stress conditions, and the increased R of SiGe pMOSFETs is mainly attributed to their lower degradation characteristic. Under real operating conditions, most of the ΔV th caused by hole trapping would be rapidly recovered through a fast recovery process, and newly-generated interface traps during the stress would determine the degradation level of V th. The SiGe pMOSFETs show lower stress-induced interface traps; thus, they would display more reliable NBTI characteristics than Si pMOSFETs under real operating conditions.

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The Improvement of High-$k$/Metal Gate pMOSFET Performance and Reliability Using Optimized Si Cap/SiGe Channel Structure

Cited by 17 publications

References 11 publications

Performance Dependence on Width-to-Length Ratio of Si Cap/SiGe Channel MOSFETs

Performance Dependence on Width-to-Length Ratio of Si Cap/SiGe Channel MOSFETs

Investigate on the Mechanism of HfO2/Si0.7Ge0.3 Interface Passivation Based on Low-Temperature Ozone Oxidation and Si-Cap Methods

Improved Degradation and Recovery Characteristics of SiGe p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors under Negative-Bias Temperature Stress

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