The Influence of Gate Bias on the Anneal of Hot-Carrier Degradation

Abstract

We observe that non-zero gate bias applied during a high temperature anneal following hot-carrier degradation (HCD) impacts degradation recovery in nFETs. The devices are arranged into custom-built arrays and fabricated in a commercial 40 nm bulk CMOS technology and the FET anneal is induced by on-chip poly-Si heaters. The anneal is modeled using Stesmans' passivation model for P b -defects in hydrogen gas (H 2 ). Negative gate bias improves the anneal, in line with studies on biased passivation of process-induced P b -defects.

Modeling of Repeated FET Hot-Carrier Stress and Anneal Cycles Using Si–H Bond Dissociation/Passivation Energy Distributions

“…The important implication of this research was that the passivation energy of HC-induced defects is not single valued, but follows a Gaussian distribution, caused by the underlying distribution in atomic defect configurations. Furthermore, in our previous work [14], we observed that negative gate bias improves HCD anneal and explained this using the dependence of the passivation of P b -defects on their charge state.…”

“…It is known that in scaled devices the Si-H bond breakage process is more complicated and can consist of a mixture of the multiple particle (MP) process and the single particle (SP) process [21]. In the former, multiple [14] 0.31 [14] 2.56 [24] 0.66 colder carriers collide with the bond and induce its vibrational excitations, increasing its energy. In the latter process, a single highly energetic carrier impinges on the bond and breaks it.…”

“…The methodology used here to measure HCD and HCD anneal on the PUF chip was established in our previous work [14] in which we investigated the influence of gate bias on HCD anneal. Since we found in our previous work that negative gate bias applied during the anneal leads to more HCD recovery, we used the most negative V gs,anneal = −0.7 V for the cycled HCD anneal measurements.…”

“…Since the whole chip sees the temperature increase during the anneal, the PGs experience high temperature while under bias and can potentially degrade during the measurement. To avoid possible effects of PG degradation, we optimized the measurement procedure as explained in [14]: i) we increased the chip V dd to 1.5 V during I−V readout to have a higher overdrive on the PGs to overcome PG degradation, ii) we focused on the evolution of the threshold voltage in the measurement instead of on the evolution of the on-current since the former metric is less sensitive to the PGs, iii) we monitored the voltage drop over the pass gates at every time step in the measurement using the sense lines on the chip and took the PG series resistance into account when calculating the FET mobility and iv) we decreased the chip V dd to 0.7 V during the anneal. For the same reason, also the periphery (shift registers) of the chip might degrade during the anneal.…”

“…integrated [9] on a chip, iii) self-heat originating from currents in the transistor [10]- [12] and iv) poly-Si heaters [13], [14].…”