The influence of the size effect of copper interconnects on RC delay variability beyond 45nm technology

Kitada, Hideki; Suzuki, Takashi; Kimura, Takahiro; Kawamura, Hiroshi; Ochimizu, H.; Okano, Shun; Tsukune, A.; Suda, Satoshi; Sakai, Satoru; Ohtsuka, N.; Tabira, T.; Shirasu, T.; Sakamoto, M.; Matsuura, Akira; Asada, Y.; Nakamura, Tomoji

doi:10.1109/iitc.2007.382333

Cited by 16 publications

(6 citation statements)

References 4 publications

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“…Global wires, on the other hand, are expected to have increasing nominal delays and larger impact on overall circuit delay due to process variations. A recent study in [7] shows considerable increase in the variation of RC delays as the wire length increases. In addition to metal layers, vias are also affected by process variations.…”

Section: Motivation and Prior Workmentioning

confidence: 97%

“…Studies predict that process variations on interconnects will have a considerable impact on critical-and long-path delays [1], [6], [7]. The reason behind these findings is that interconnects are not only the dominant contributor to overall path delays, they are also susceptible to large process variations due to lithography effects, etching, gradients, and various random effects [8].…”

Section: Motivation and Prior Workmentioning

confidence: 99%

“…Considering the library parameters, we assumed that M5 and M6 are global routing layers and all other metal layers are used for local routing. We used a delay variation of 30% on local wires and 10% on global wires, which increases with wire length as predicted in [7]. The effect of delay Paper 28.3…”

Section: B Generating Ddpms For Gate Instances and Interconnectsmentioning

confidence: 99%

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Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects

Yilmaz

Chakrabarty

Tehranipoor

2008

2008 IEEE International Test Conference

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Section: Motivation and Prior Workmentioning

confidence: 97%

Section: Motivation and Prior Workmentioning

confidence: 99%

Section: B Generating Ddpms For Gate Instances and Interconnectsmentioning

confidence: 99%

See 1 more Smart Citation

Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects

Yilmaz

Chakrabarty

Tehranipoor

2008

2008 IEEE International Test Conference

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“…Example of the dependence of sheet resistance on line width can be seen in Figure 13. Kitada et al [42] investigated grain size distribution dependence on the line width and height of 45 nm and 32 nm copper lines. They found that the grain size was proportional to the logarithm of the line width.…”

Section: Metal Width and Space Rulesmentioning

confidence: 99%

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Shauly

2018

JLPEA

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The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 µm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations.Keywords: back end of line; layout design rules; copper technology; inter-metal dielectric time-dependent dielectric breakdown (IMD-TDDB) M2-M5) have similar or slightly increased thicknesses when compared with the M1 layer, and are mostly used for connections between various devices. Semi-global (M6-M7, 0.35-0.9 µm) and global (M8, 0.9-3.3 µm) lines are used for power buses, transmission lines, and inductors.In order to achieve a tight pitch of M1 and semi-global lines with a high-density design, interconnects are used to connect high-density-logic transistors, standard cells, and other functional blocks in a system on chip (SoC). In general, application-specific integrated circuits (ASICs) and SoCs tend to use a combination of interconnect metals with a large number of MI lines (semi-global) for applications such as highly parallel graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and multi-core smartphone processors (multiple central processing unit (CPU) and GPU cores). In contrast, devices for applications of radio frequency CMOS (RFCMOS), millimeter wave (mmWave), and WiFi use several layers of semi-global and global lines for inductors, transmission lines, and more. From a practical point of view, the set of rules relating to specific types of interconnect do not change based on their use in various applications. This is because many electronic design automation (EDA) tools such as design rule checks (DRCs), BEOL RC modeling, and even dummy fill insertions also need to be adjusted. Instead, the platform process design kit (PDK) includes a large set of metal combinations so that the designer may select one based on their integrated circuit (IC) needs. For example, WiFi ICs, designed using the 65 nm RFCMOS...

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“…Environmental factors that occur during chip operation include power supply variations and temperature changes across the chip. Physical factors affected during fabrication include various parameters but they are not limited to interconnect line-width [5][6][7], metallic grain size [8][9][10] and transistor channel length [11][12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

Propagation delay deviations due to process induced line parasitic variations in global VLSI interconnects

Verma

Singh

Kaushik

et al. 2011

2011 IEEE Recent Advances in Intelligent Computational Systems

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Process variation in current nanometer regime has recently emerged as a major concern in the design of very large scale integrated (VLSI) circuits including interconnect. Process variation leads to many uncertainties on circuit performances such as propagation delay. With the shrinking channel dimensions of MOSFET to nanometer scale, the performance of VLSI/ULSI chip becomes less predictable. The predictability of circuit performance may be reduced due to poor control of the physical features of devices and interconnects during the manufacturing process. Variations in these quantities maps to variations in the electrical behavior of circuits. The interconnect line resistance and capacitance varies due to changes in interconnect width and thickness, substrate, implant impurity level, and surface charge. This paper presents the variation of propagation delay through driver-interconnect-load (DIL) system due to various effects of interconnect parasitic. The impact of process induced variations on propagation delay of the circuit is discussed for three different fabrication technologies of 130nm, 70nm and 45nm. The comparison between these three technologies extensively shows that the effect of line resistive and capacitive parasitic variations on propagation delay has almost uniform trend as feature size shrinks. However, resistive parasitic variation in global interconnects has very nominal effect on the propagation delay as compared to capacitive parasitic. Propagation delay variation is observed from 0.01% to 0.04% and -4.32% to 18.1% due to resistive and capacitive deviation of -6.1% to 25% respectively.

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The influence of the size effect of copper interconnects on RC delay variability beyond 45nm technology

Cited by 16 publications

References 4 publications

Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects

Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Propagation delay deviations due to process induced line parasitic variations in global VLSI interconnects

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