The Influence of Uniaxial Normal Stress on the Performance of Vertical Bipolar Transistors

Abstract

In this paper, we have explored the response of bipolar junction transistors (BJT) to the controlled application of mechanical stress. Mechanical strains and stresses are developed during the fabrication, assembly and packaging of the integrated circuit (IC) chips. Due to these stresses and strains, it has been observed by many researchers that changes can occur in the electrical performance of both analog and digital devices. Stress-induced device parametric shifts affect the performance of analog circuits that depend upon precise matching of bipolar and/or MOS devices, and can cause them to operate out of specifications. In the past the authors have extensively investigated the stress effects on resistors embedded on integrated chips and were successful in characterizing die stresses for various packaging architectures. We have also observed stress effects on diodes, field effect transistors (FETs), van der Pauw structures and CMOS sensor arrays. In this present work, the stress dependence of the electrical behavior of bipolar transistors has been investigated. Test structures have been utilized to characterize the stress sensitivity of vertical bipolar devices fabricated on (100) silicon wafers. In the experiments, uniaxial normal stresses were applied to silicon wafer strips using a four-point-bending fixture. An approximate theory has also been developed for stress-induced changes in the current gain of bipolar junction transistors. Both the theoretical and experimental results show similar trend for DC current gain vs. stress plots. Multi-Physics based finite element simulations (coupled electro-mechanical-thermal) have been performed to understand the device level mechanisms that cause the stress induced changes in the BJTs and also to characterize and model stress dependence of fundamental silicon material parameters such as bandgap, intrinsic carrier concentration, and electron/hole mobilities. In the future, the developed formulations can be applied to theoretically optimize transistor design, placement, orientation, and processing to minimize the impact of fabrication and packaging induced die stresses.

High sensitive, linear and thermostable pressure sensor utilizing bipolar junction transistor for 5 kPa

“…It is possible due to the BJT three-pole contact connection. One of development directions of similar PDA-NFL electrical circuits is the use of deformable or non-deformable metal-oxide-semiconductor transistors (MOSFETs) or junction gate field-effect transistors (JFETs) instead of BJT and change of PDA-NFL electrical circuit to more complex combinations [28][29][30][31][32][33][34][35] in the future. The use of active elements complicates both the design and fabrication of pressure sensor chip because competent integration of MEMS and CMOS processes is necessary [36].…”

High Sensitive, Linear and Thermostable Pressure Sensor Utilizing Bipolar Junction Transistor for 5 kPa

“…It is possible due to the BJT three-pole contact connection. One of development directions of similar PDA-NFL electrical circuits is the use of deformable or nondeformable metal-oxide-semiconductor transistors (MOSFETs) or junction gate field-effect transistors (JFETs) instead of BJT and change of PDA-NFL electrical circuit to more complex combinations [26][27][28][29][30][31][32] in the future. The use of active elements complicates both the design and fabrication of pressure sensor chip because competent integration of MEMS and CMOS processes is necessary [33].…”