The MasPar MP-1 architecture

Blank, Tom

doi:10.1109/cmpcon.1990.63648

Cited by 192 publications

(66 citation statements)

References 4 publications

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“…As a result the algorithms are well-suited for SIMD architectures, such as the Connection Machine [11] or MasPar (4]. The O(ClogN) with high probability bound holds because we have assumed that a fast probabilistic parallel algorithm [18] is used to solve a certain trapezoidal decomposition problem (Sections 2, 5).…”

Section: Iavail And/or S Speolalmentioning

confidence: 99%

Massively parallel algorithms for trace-driven cache simulations

Nicol

Greenberg

Lubachevsky

1994

IEEE Trans. Parallel Distrib. Syst.

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Trace-driven cache simulation is central to computer design. A trace is a very long sequence, zi, .... ZNj, of references to lines (contiguous locations) from main memory. At the t t h instant, reference z is hashed into a set of cache locations, the contents of which are then compared with Zt. If at the tth instant xt is not present in the cache, then it is said to be a miil and is loaded into the cache set, possibly forcing the replacement of some other memory line, and mak,.ig z, present for the (t + 1)" instant. The problem of parallel simulation of a subtrace of N references directed to a C line cache set Is considered, with the aim of determining which references are misses and related statistics.A simulation method is presented for the Least-Recently-Used (LRU) policy, which regardless of the set size C runs in time O(log N) using N processors on the exclusive read, exclusive write (EREW) parallel model. A simpler LRU simulation algorithm is given that runs in O(C log N) time using N/log N processors. We present timings of the second algorithm's implementation on the MasPar MP-1, a machine with 16384 processors. A broad class of reference-baaed line replacement policies are considered, which includes LRU as well as the Least-Frequently-Used and Random replacement policies. A simulation method is presented for any such policy that on any trace of length N directed to a C line set runs in time O(C log N) time with high probability using N processors on the EREW model. The algorithms are simple, have very little space overhead, and are well-suited for SIMD implementation.

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Section: Iavail And/or S Speolalmentioning

confidence: 99%

Massively parallel algorithms for trace-driven cache simulations

Nicol

Greenberg

Lubachevsky

1994

IEEE Trans. Parallel Distrib. Syst.

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“…These predated high density semiconductor integration but explored the potential performance opportunities of intimate association of logic and memory in single structures. STARAN [1] is one example of example of such architectures followed by other SIMD architectures as the Goodyear MPP [2], the MasPar MP-1 & MP-2 [3,4], and the TMC CM-2 [5].…”

Section: Related Research In the Fieldmentioning

confidence: 99%

The “MIND” scalable PIM architecture

Sterling

Brodowicz

2005

Grid Computing the New Frontier of High Performance Computing

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MIND (Memory, Intelligence, and Network Device) is an advanced parallel computer architecture for high performance computing and scalable embedded processing. It is a Processor-in-Memory (PIM) architecture integrating both DRAM bit cells and CMOS logic devices on the same silicon die. MIND is multicore with multiple memory/processor nodes on each chip and supports global shared memory across systems of MIND components. MIND is distinguished from other PIM architectures in that it incorporates mechanisms for efficient support of a global parallel execution model based on the semantics of message-driven multithreaded split-transaction processing. MIND is designed to operate either in conjunction with other conventional microprocessors or in standalone arrays of like devices. It also incorporates mechanisms for fault tolerance, real time execution, and active power management. This paper describes the major elements and operational methods of the MIND architecture.

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“…However, there are several problems which require non local communications. Some massively parallel machines [15] [8] have a scheme to cover such communication patterns. But, they integrate a static ICN.…”

Section: Related Workmentioning

confidence: 99%

Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip

Baklouti

Marquet

Dekeyser

et al. 2010

Lecture Notes in Computer Science

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Abstract. The SIMD parallel systems play a crucial role in the field of intensive signal processing. For most the parallel systems, communication networks are considered as one of the challenges facing researchers. This work describes the FPGA implementation of two reconfigurable and flexible communication networks integrated into mppSoC. An mppSoC system is an SIMD massively parallel processing System on Chip designed for data-parallel applications. Its most distinguished features are its parameterization and the reconfigurability of its interconnection networks. This reconfigurability allows to establish one configuration with a network topology well mapped to the algorithm communication graph so that higher efficiency can be achieved. Experimental results for mppSoC with different communication configurations demonstrate the performance of the used reconfigurable networks and the effectiveness of algorithm mapping through reconfiguration.

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The MasPar MP-1 architecture

Cited by 192 publications

References 4 publications

Massively parallel algorithms for trace-driven cache simulations

Massively parallel algorithms for trace-driven cache simulations

The “MIND” scalable PIM architecture

Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip

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