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Sleep is an important part of our lives which affects many life factors such as memory, learning, metabolism and the immune system. Researchers have found correlations between sleep and several diseases such as Chronic Obstructive Pulmonary disease, Chronic Heart Failure, Alzheimer's disease, etc. However, sleep data is mainly recorded and diagnosed in sleep labs or in hospitals for some critical cases with high costs.In this work we develop a non-invasive, wearable neck-cuff system capable of real-time monitoring and visualization of physiological signals. These signals are generated from various sensors housed in a soft neck-worn collar and sent via Bluetooth to a cell phone which stores the data. This data is processed and reported to the user or uploaded to the cloud and/or to a local PC. With this system we are able to monitor people's sleep continuously in a non-invasive and low cost method while at the same time collect a large database for sleep data which may benefit future advances in new findings and possibly enable a diagnosis of other diseases. We show as one of the applications of our system the possible detection of obstructive sleep apnea which is a common sleep disorder.

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Stanford University and Xerox PARC Stanford, California and Palo Alto, California Bit maps have been used in many Design Automation (DA) algorithms such as printed circuit board (PCB) layout and integrated circuit (IC) design rule checking ('DRC). The attraction of bit maps is that they provide a direct representation of two-dimensional images. The difficulty with large so:ale use of bit maps (e.g., for DRC on VLSI) is that the large amounts of data can consume impractical amounts of computation on sequential machines. This paper describes a processing archilecture that is specifically designed to operate on bit maps. It has an inherently two-dimensional construction and has a very large parallel processing capability.Also included in tiffs paper are descriptions of algorithms that exploit the architecture.Algnrithms for routing, DRC, and bit vector manipulation are included, large amounts of data; a miss match between conventional word based computers and required bit operations on two dimensional data structures.It should be noted that bit map processing architectures have been proposed since 1958 [9] for image processing applications. Recently, machines have been reported by Reeves [6,7] and l)nff [2,3]. ltowever, in all the earlier work, a large scale implementation was problematic.We describe a physical chip design that can be integrated into a large scale bit processing architecture. The approach is to incorporate one processing element into each node of a bit map. The scheme is called SAM for synchronous active memory. In the following sections, the operation of one SAM cell, tile overall SAM architecture, algorithms and future work arc described. IntroductionAs the size of design problems increases, the computational time rcquirecl by the suftwarc tools also increases. Unfortunately, many I)A programs have a nnn-linear run time dependence on the size of tile design problem. Current size problems often require run times of several h{a;rs. For example, PCB routing for a 10 x 10 inch board with 100 lC's and I)I~.C on a 200 x 200 rail integrated circuit require several hours of CPU time on a medium-sized processor.There are a number of possible solutions to the size vs. execution time problem. The most obvious solution is to use faster and larger computers with the same programs. This ~q~proach is doomed to failure for two reasons: very large cost of large systems; tile problem size may increase beyond the capability of the machine. Unfortunately, the speed of large mainframes is not increasing as fast as the increase in problem size and commensurate non-linear increase in execution time. Another possible solution is to build special purpose hardware that physically implements an algorithm. The I.ee routing algorithm is an example that has been implemented with dedicated hardware. However, this approach also has weaknesses: no flexibility to adapt to changing technology, large expense due to low volume of the device and limited useful lifetime.Reasonable solutions to the size vs. execution problem are...