Designers of MOS LSI circuits can take advantage of complex functional cells in order to achieve better performance . This paper discusses the implemention of a random logic function on an array of CMOS transistors . A graph-theoretical algorithm which minimizes the size of an array is presented . This method is useful for the design of cells used in conventional design automat ion systems .-iNDEX TERMS: CMOS func tional arrays , CMOS circuit design , LSI layou t , LSI design automation , computer-aided design , design au tomat ion 1.

Stanford University and Xerox PARC Stanford, California and Palo Alto, California Bit maps have been used in many Design Automation (DA) algorithms such as printed circuit board (PCB) layout and integrated circuit (IC) design rule checking ('DRC). The attraction of bit maps is that they provide a direct representation of two-dimensional images. The difficulty with large so:ale use of bit maps (e.g., for DRC on VLSI) is that the large amounts of data can consume impractical amounts of computation on sequential machines. This paper describes a processing archilecture that is specifically designed to operate on bit maps. It has an inherently two-dimensional construction and has a very large parallel processing capability.Also included in tiffs paper are descriptions of algorithms that exploit the architecture.Algnrithms for routing, DRC, and bit vector manipulation are included, large amounts of data; a miss match between conventional word based computers and required bit operations on two dimensional data structures.It should be noted that bit map processing architectures have been proposed since 1958 [9] for image processing applications. Recently, machines have been reported by Reeves [6,7] and l)nff [2,3]. ltowever, in all the earlier work, a large scale implementation was problematic.We describe a physical chip design that can be integrated into a large scale bit processing architecture. The approach is to incorporate one processing element into each node of a bit map. The scheme is called SAM for synchronous active memory. In the following sections, the operation of one SAM cell, tile overall SAM architecture, algorithms and future work arc described. IntroductionAs the size of design problems increases, the computational time rcquirecl by the suftwarc tools also increases. Unfortunately, many I)A programs have a nnn-linear run time dependence on the size of tile design problem. Current size problems often require run times of several h{a;rs. For example, PCB routing for a 10 x 10 inch board with 100 lC's and I)I~.C on a 200 x 200 rail integrated circuit require several hours of CPU time on a medium-sized processor.There are a number of possible solutions to the size vs. execution time problem. The most obvious solution is to use faster and larger computers with the same programs. This ~q~proach is doomed to failure for two reasons: very large cost of large systems; tile problem size may increase beyond the capability of the machine. Unfortunately, the speed of large mainframes is not increasing as fast as the increase in problem size and commensurate non-linear increase in execution time. Another possible solution is to build special purpose hardware that physically implements an algorithm. The I.ee routing algorithm is an example that has been implemented with dedicated hardware. However, this approach also has weaknesses: no flexibility to adapt to changing technology, large expense due to low volume of the device and limited useful lifetime.Reasonable solutions to the size vs. execution problem are...

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New placement algorithms have been developed which are suitable for the layout of Very